An Efficient Implementation of Arbiter PUF on FPGA for IoT Application

Mahalat, Mahabub Hasan; Mandal, Suraj; Mondal, Anindan; Sen, Bibhash

doi:10.1109/socc46988.2019.1570548268

Cited by 21 publications

(8 citation statements)

References 11 publications

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“…Considerable research contributions are found in achieving symmetrical routing between the switching blocks. The various configurations of SB design include employing MUX primitives [33]- [35], PDL logic [32], [36], a 6-2 input LUT combining two parallel MUX in one LUT [37], PDL and MUX without cross-coupling [38], tri-state buffers [39], and PCS (Path Changing Switch) [40] focusing on response bias and enhanced uniqueness. A Schmitt trigger has been used as a buffer between the switch blocks instead of a CMOS buffer as it is susceptible to process variations in [41].…”

Section: B Implementation Of Switch Blockmentioning

confidence: 99%

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Hemavathy

Bhaaskaran

2023

IEEE Access

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Hardware security modules play a crucial role in protecting and preserving technologically integrated systems that are used in daily life. They employ cryptographic protocols to secure a system against adversaries. Generally, cryptographic algorithms and security keys are quintessential for maintaining the security of a system. Cryptography uses a secret key to encipher and decipher the data. These secret keys are stored in a non-volatile memory that attackers can easily access. The hardware security primitive, Physical Unclonable Function (PUF) is a promising alternative for enhancing the security of interconnected devices. A PUF produces an output in response to an input based on physical structure and intrinsic manufacturing variations of an integrated circuit (IC). The generated random response being unpredictable, act as a robust secret key in cryptographic protocols. The first silicon PUF is the Arbiter PUF, which can instantly produce significantly more secret keys based on the input with a lightweight design. Due to its advantage, it is best suited for device authentication in resource-constrained applications employing the Internet of Things (IoT). The PUF is also suitable for applications such as the Internet of Vehicles, the Internet of Medical Things, RFID tags, and smart cards. In this paper, the basic Arbiter PUF design is implemented in ZedBoard to analyze the PUF performance characteristics for 16, 32, and 64-bit responses. A review of Arbiter PUF design, different compositions of Arbiter PUF, their individual characteristics, and vulnerabilities against machine-learning attacks have been presented at their broader best in this paper.

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Section: B Implementation Of Switch Blockmentioning

confidence: 99%

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Hemavathy

Bhaaskaran

2023

IEEE Access

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“…• Silicon: These rely on the uncontrollable differences in manufacturing between devices and do not require extra components outside of an FPGA. This category can further be broken up into delay-based PUFs, such as Arbiter PUFs [19,20] and RO PUFs [21][22][23][24], and memory-based PUFs, which utilize the entropy from volatile memory cells [25,26]. • Non-silicon: These PUFs are constructed using peripherals besides FPGA silicon for sources of entropy.…”

Section: Physically Unclonable Functionsmentioning

confidence: 99%

“…An encryptor should reduce this correlation to zero, indicating that two ciphers are entirely unique. Equation (20) shows how the PCC is calculated, where M is the total number of pixels, x i represents a pixel value on image x at index m, y i represents a pixel from a similar image tested against image x at index m, and x and ȳ represent the mean values of pixel intensities in images x and y, respectively.…”

Section: Differential Attack Analysismentioning

confidence: 99%

Integrating Lorenz Hyperchaotic Encryption with Ring Oscillator Physically Unclonable Functions (RO-PUFs) for High-Throughput Internet of Things (IoT) Applications

Magyari,

Chen

2023

Electronics

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With the combined call for increased network throughput and security comes the need for high-bandwidth, unconditionally secure systems. Through the combination of true random number generators (TRNGs) for unique seed values, and four-dimensional Lorenz hyperchaotic systems implemented on a Stratix 10 Intel FPGA, we are able to implement 60 MB/s encryption/decryption schemes with 0% data loss on an unconditionally secure system with the NIST standard using less than 400 mW. Further, the TRNG implementation allows for unique encryption outputs for similar images while still enabling proper decryption. Histogram and adjacent pixel analysis on sample images demonstrate that without the key, it is not possible to extract the plain text from the encrypted image. This encryption scheme was implemented via PCIe for testing and analysis.

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“…Regarding cost-effective and efficient solutions, and considering that IoT devices are often limited in resources, reconfigurable devices such as Field-Programmable Gate Arrays (FPGAs) and programmable Systems-on-Chips (SoCs) have established themselves as technological allies to perform specific functions in a compact and efficient manner, which makes them suitable for portable and battery-powered devices for usages in which power consumption is a critical factor. Two additional features that make FPGAs and SoCs suitable for IoT devices are that they offer scalability and flexibility to be reprogrammed on site, significantly shortening development time and maintenance costs [10][11][12][13].…”

Section: Introductionmentioning

confidence: 99%

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices

Rojas-Muñoz

Sánchez-Solano

Martínez-Rodríguez

et al. 2023

Sensors

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The proliferation of devices for the Internet of Things (IoT) and their implication in many activities of our lives have led to a considerable increase in concern about the security of these devices, posing a double challenge for designers and developers of products. On the one hand, the design of new security primitives, suitable for resource-limited devices, can facilitate the inclusion of mechanisms and protocols to ensure the integrity and privacy of the data exchanged over the Internet. On the other hand, the development of techniques and tools to evaluate the quality of the proposed solutions as a step prior to their deployment, as well as to monitor their behavior once in operation against possible changes in operating conditions arising naturally or as a consequence of a stress situation forced by an attacker. To address these challenges, this paper first describes the design of a security primitive that plays an important role as a component of a hardware-based root of trust, as it can act as a source of entropy for True Random Number Generation (TRNG) or as a Physical Unclonable Function (PUF) to facilitate the generation of identifiers linked to the device on which it is implemented. The work also illustrates different software components that allow carrying out a self-assessment strategy to characterize and validate the performance of this primitive in its dual functionality, as well as to monitor possible changes in security levels that may occur during operation as a result of device aging and variations in power supply or operating temperature. The designed PUF/TRNG is provided as a configurable IP module, which takes advantage of the internal architecture of the Xilinx Series-7 and Zynq-7000 programmable devices and incorporates an AXI4-based standard interface to facilitate its interaction with soft- and hard-core processing systems. Several test systems that contain different instances of the IP have been implemented and subjected to an exhaustive set of on-line tests to obtain the metrics that determine its quality in terms of uniqueness, reliability, and entropy characteristics. The results obtained prove that the proposed module is a suitable candidate for various security applications. As an example, an implementation that uses less than 5% of the resources of a low-cost programmable device is capable of obfuscating and recovering 512-bit cryptographic keys with virtually zero error rate.

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An Efficient Implementation of Arbiter PUF on FPGA for IoT Application

Cited by 21 publications

References 11 publications

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Arbiter PUF—A Review of Design, Composition, and Security Aspects

Integrating Lorenz Hyperchaotic Encryption with Ring Oscillator Physically Unclonable Functions (RO-PUFs) for High-Throughput Internet of Things (IoT) Applications

On-Line Evaluation and Monitoring of Security Features of an RO-Based PUF/TRNG for IoT Devices

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