An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing

Ataie, Roghayeh; Zarandi, Azadeh Alsadat Emrani; Mehrabani, Yavar Safaei

doi:10.1080/00207217.2019.1576232

Cited by 18 publications

(19 citation statements)

References 11 publications

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“…It is considered as an important criterion for estimating efficiency of an inexact FA, which aims to reduce not only delay and power but also transistor count and TED. Therefore, such a comprehensive evaluating factor can truly reflect the efficiency of an approximate FA (Mehrabani et al , 2017; Ataie et al , 2019). …”

Section: Transistor-level and Application-level Simulation Resultsmentioning

confidence: 99%

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High-Performance CML approximate full adders for image processing application of laplace transform

Uoosefian

Navi

Mirzaee

et al. 2020

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Purpose The high demand for fast, energy-efficient, compact computational blocks in digital electronics has led the researchers to use approximate computing in applications where inaccuracy of outputs is tolerable. The purpose of this paper is to present two ultra-high-speed current-mode approximate full adders (FA) by using carbon nanotube field-effect transistors. Design/methodology/approach Instead of using threshold detectors, which are common elements in current-mode logic, diodes are used to stabilize voltage. Zener diodes and ultra-low-power diodes are used within the first and second proposed designs, respectively. This innovation eliminates threshold detectors from critical path and makes it shorter. Then, the new adders are employed in the image processing application of Laplace filter, which detects edges in an image. Findings Simulation results demonstrate very high-speed operation for the first and second proposed designs, which are, respectively, 44.7 per cent and 21.6 per cent faster than the next high-speed adder cell. In addition, they make a reasonable compromise between power-delay product (PDP) and other important evaluating factors in the context of approximate computing. They have very few transistors and very low total error distance. In addition, they do not propagate error to higher bit positions by generating output carry correctly. According to the investigations, up to four inexact FA can be used in the Laplace filter computations without a significant image quality loss. The employment of the first and second proposed designs results in 42.4 per cent and 32.2 per cent PDP reduction compared to when no approximate FA are used in an 8-bit ripple adder. Originality/value Two new current-mode inexact FA are presented. They use diodes as voltage regulators to design current-mode approximate full-adders with very short critical path for the first time.

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Section: Transistor-level and Application-level Simulation Resultsmentioning

confidence: 99%

“…Ataie et al (2019) have presented two CNFET-based inexact FAs (10TIFA and 6TIFA). As it is shown in Figure 9, they use capacitive threshold logic (CTL) to generate output signals.…”

Section: Literature Reviewmentioning

confidence: 99%

High-Performance CML approximate full adders for image processing application of laplace transform

Uoosefian

Navi

Mirzaee

et al. 2020

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“…This can reduce the influence of noise and simplify the calculation of the identification part. In this section, we use the full threshold binarization method to process the image [16]. The global binarization threshold selection steps are as follows.…”

Section: Binary Imagementioning

confidence: 99%

LPI Radar Waveform Recognition Based on CNN and TPOT

2019

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The electronic reconnaissance system is the operational guarantee and premise of electronic warfare. It is an important tool for intercepting radar signals and providing intelligence support for sensing the battlefield situation. In this paper, a radar waveform automatic identification system for detecting, tracking and locating low probability interception (LPI) radar is studied. The recognition system can recognize 12 different radar waveform: binary phase shift keying (Barker codes modulation), linear frequency modulation (LFM), Costas codes, polytime codes (T1, T2, T3, and T4), and polyphase codes (comprising Frank, P1, P2, P3 and P4). First, the system performs time–frequency transform on the LPI radar signal to obtain a two-dimensional time–frequency image. Then, the time–frequency image is preprocessed (binarization and size conversion). The preprocessed time–frequency image is then sent to the convolutional neural network (CNN) for training. After the training is completed, the features of the fully connected layer are extracted. Finally, the feature is sent to the tree structure-based machine learning process optimization (TPOT) classifier to realize offline training and online recognition. The experimental results show that the overall recognition rate of the system reaches 94.42% when the signal-to-noise ratio (SNR) is −4 dB.

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“…To implement the majority function, the CTL logic is used to save the number of transistors (Safaei Mehrabani and Eshghi, 2015; Ataie et al , 2019). In this logic, to implement the 3-input majority function, a 3-input capacitive network with two conventional inverter gates ( V inv = V dd /2) is used.…”

Section: Proposed Inexact 4:2 Compressormentioning

confidence: 99%

A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology

Mehrabani

Bagherizadeh

Shafiabadi

et al. 2019

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Purpose This paper aims to present an inexact 4:2 compressor cell using carbon nanotube filed effect transistors (CNFETs). Design/methodology/approach To design this cell, the capacitive threshold logic (CTL) has been used. Findings To evaluate the proposed cell, comprehensive simulations are carried out at two levels of the circuit and image processing. At the circuit level, the HSPICE software has been used and the power consumption, delay, and power-delay product are calculated. Also, the power-delaytransistor count product (PDAP) is used to make a compromise between all metrics. On the other hand, the Monte Carlo analysis has been used to scrutinize the robustness of the proposed cell against the variations in the manufacturing process. The results of simulations at this level of abstraction indicate the superiority of the proposed cell to other circuits. At the application level, the MATLAB software is also used to evaluate the peak signal-to-noise ratio (PSNR) figure of merit. At this level, the two primary images are multiplied by a multiplier circuit consisting of 4:2 compressors. The results of this simulation also show the superiority of the proposed cell to others. Originality/value This cell significantly reduces the number of transistors and only consists of NOT gates.

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An efficient inexact Full Adder cell design in CNFET technology with high-PSNR for image processing

Cited by 18 publications

References 11 publications

High-Performance CML approximate full adders for image processing application of laplace transform

High-Performance CML approximate full adders for image processing application of laplace transform

LPI Radar Waveform Recognition Based on CNN and TPOT

A low-PDAP and high-PSNR approximate 4:2 compressor cell in CNFET technology

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