An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding

Elhamzi, Wajdi; Dubois, Julien; Mitéran, Johel; Atri, Mohamed

doi:10.1007/s11554-012-0274-5

Cited by 16 publications

(9 citation statements)

References 20 publications

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“…It utilizes 27,608 LUTs, 20,233 register bits, 5 blocks SRAMs are used to store the SW and the 16 × 16 current block. [7,17,21] The first selected architecture Table 1. It can process 1080HD video streams at that clock frequency.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…It can process 1080HD video streams at that clock frequency. [21] When compared to the architecture in [7], the proposed work considerably decreases the latency by fifth from 4096, the use of three parallel processor modules in our approach requires more resources such as LUTs compared to [7], the maximum operating frequency is slightly increased and the search range has risen from 16 × 16 to 48 × 48. Table 3 shows the comparison between our proposed architecture of IME based on Virtex 7 FPGA, and previously published ME architectures based on ASIC and FPGA platforms.…”

Section: Implementation Resultsmentioning

confidence: 99%

“…[4] The significant improvement on coding efficiency of H.264/ AVC comes mainly from the combination of large and complex prediction methods and multiple profiles and tools to meet the various requirements in video applications. [7] The benefits of full-search algorithms appear in offering high video quality and high compression ratios since exhaustive search guarantees optimal results when considering all possible positions. These two objectives greatly increase the computational complexity of the ME algorithm, this high complexity prevents software implementations on most of microprocessors to achieve realtime processing.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Yahi

Messaoudi

Toumi

et al. 2015

International Journal of Computers and Applications

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a lerICa laboratory, Badji mokhtar university, annaba, algeria; b le2I laboratory, Burgundy university, dijon, france ABSTRACT Nowadays, H.264/AVC reaches very high resolutions, flexible depending on the application, which particularly leads to a very large amount of data compression. The motion estimation defines the most-complex process and the most interesting at the same time; its complexity appears with a consumption of more than 60% of total encoding time which make it difficult to achieve real-time encoding required in many video applications, but the interesting part is the flexibility to make its implementation variant according to the application. For this purpose, the following paper presents a speed real-time hardware implementation of integer motion estimation used in H.264/AVC, the method is based on the full-search block-matching algorithm. The proposed architecture calculates best motion vector using a parallel process. It is composed of three processor modules and a comparator three values. Implementation results based on Field Programmable Gate Array devices uses Xilinx Virtex7 XC7VX550T show performance characteristics like low latency, high processing speed reaching 473 MHz of frequency. The processing capacity is up to 1080HD video streams with a search range of 48 × 48.

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Section: Implementation Resultsmentioning

confidence: 99%

Section: Implementation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Yahi

Messaoudi

Toumi

et al. 2015

International Journal of Computers and Applications

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“…The Fractural ME algorithm provides the ME sub pixel accuracy of smart camera that used in accelerators. This algorithm improves the computation intensive [5][6][7]. With the help of fast search algorithm, most of the ME has been performed.…”

Section: Introductionmentioning

confidence: 99%

VLSI Implementation of Motion Estimation Using Level Convertor with CSLA Adder

Sakhare¹

2019

IJIES

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Nowadays, Motion Estimation (ME) plays a vital role in traffic signals, movie making, and security purpose to identify the motion of an object. In this paper, Smart and Low power (SLP) based ME is introduced with Level Convertor and Carry SeLect Adder (LC-CSLA-ME). Normal SLP architecture requires more power for performing ME, but in the LC-CSLA-ME architecture, 0.9v supply voltage is used to carry-out the ME. The LC is used to supply the required voltage to the respective sub blocks, which helps to reduce the power consumption of the overall architecture. Instead of using normal adder, CSLA adder is used in prediction and classification unit for improving the hardware utilization. The performance of Application Specified Integrated Chips (ASIC) and Field Programmable Gate Array (FPGA) analysed for both existing and proposed methods. In 180nm technology, LC-CSLA-ME architecture occupied 0.065mm 2 area, 2.10mW power, and 104ms delay. The different dataset such as Johnny, Vidyo 1, and Vidyo 4 is analysed for ME. The Coding Time Saving (CTS) evaluated for both existing and LC-CSLA-ME architectures. In the LC-CSLA-ME, average CTS of Operating Power Points (OPP1, OPP2, OPP3, OPP4, and OPP5) are 34.021, 54.316, 67.021, 75.027, and 80.071 that is high compared to the existing methods.

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“…Indeed, a video compression step may be included into the smart camera to reduce data-bandwidth using high compression ratio except when a fall is detected. The SoC architecture will allow, infine, the inclusion of the camera the hardware accelerator dedicated to the motion estimation for video coding we designed simultaneously with the fall detection algorithm development [11] in the camera. Moreover, such a heterogeneous platform is an ideal candidate to evaluate different architecture configurations during the design space exploration phase.…”

Section: Introductionmentioning

confidence: 99%

Fast prototyping of a SoC-based smart-camera: a real-time fall detection case study

Senouci

Charfi

Heyrman

et al. 2014

J Real-Time Image Proc

Self Cite

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Smart camera, i.e. cameras that are able to acquire and process images in real-time, is a typical example of the new embedded computer vision systems. A key example of application is automatic fall detection, which can be useful for helping elderly people in daily life. In this paper, we propose a methodology for development and fast-prototyping of a fall detection system based on such a smart camera, which allows to reduce the development time compared to standard approaches. Founded on a supervised classification approach, we propose a HW/SW implementation to detect falls in a home environment using a single camera and an optimized descriptor adapted to real-time tasks. This heterogeneous implementation is based on Xilinx's system-on-chip named Zynq. The main contributions of this work are (i) the proposal of a codesign methodology. These methodologies enable the HW/ SW partitioning to be delayed using high-level algorithmic description and high-level synthesis tools. Our approach enables fast prototyping which allows fast architecture exploration and optimisation to be performed, (ii) the design of a hardware accelerator dedicated to boostingbased classification, which is a very popular and efficient algorithm used in image analysis, (iii) the proposal of falldetection embedded in a smart camera and enabling integration into the elderly people environment. Performances of our system are finally compared to the state-of-the-art.

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An efficient low-cost FPGA implementation of a configurable motion estimation for H.264 video coding

Cited by 16 publications

References 20 publications

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

Real-time hardware implementation of a speed FSBMA used in H.264/AVC

VLSI Implementation of Motion Estimation Using Level Convertor with CSLA Adder

Fast prototyping of a SoC-based smart-camera: a real-time fall detection case study

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