An efficient memory block selection strategy to improve the performance of cache memory subsystem

Abstract

Although cache improves performance by reducing the speed-gap between the CPU and main memory, cache increases the timing unpredictability due to its dynamic nature. Cache also requires signi cant amount of power to be operated. Unpredictability and power consumption become even worse in multicore systems due the presence of multiple levels of caches. Recent studies indicate that predictability can be increased and total power consumption can be decreased without compromising performance by locking appropriate memory blocks. The su ccess of cache locking depends on the accurate selection of blocks to be locked. In this work, we propose an easy but e cient memory block selection strategy to enhance cache locking and cache replacement enactment and overall cache memory subsystem performance. Proposed scheme determines the blocks that produce more cache misses if not locked and stores the block address and miss information (BAMI) at cache level. Cache locking technique should lock memory blocks with higher cache misses and cache replacement policy should select victim blocks with lower cache misses using BAMI. We simulate single-core and multicore systems, both with two-level cache memory subsystem, to evaluate the proposed block selection scheme. Experimental results show that the predictability can be improved by increasing hit ratio up to 11% and total power consumption can be decreased up to 20% by using our memory block selection scheme.

Performance Evaluation of Multicore Cache Locking using Multimedia Applications

“…However, aggressive cache locking may decrease the performance/power ratio due to the reduction of the effective cache size. In both CL1 and CL2 cache locking, we lock 25% of the cache size (as suggested in [9]) and randomly select the blocks to be locked. Some important simulation results are presented in the following subsections.…”

“…In [9], an efficient memory block selection strategy is presented that can be used to improve the performance of cache memory subsystem. The selected blocks should produce more misses if not locked.…”

“…We obtain the average delay per task and total power consumed by the system for no locking, CL1 locking, and CL2 locking. Based on the suggestion made in [9], we lock up to 25% of the cache size in order to achieve the maximum performance gain. In the simulation, we randomly select the blocks to be locked.…”

“…Cache locking is introduced in single-core systems to increase the execution time predictability [9]- [19]. Cache locking is the ability to prevent some or all of the cache blocks from being overwritten during runtime.…”

Improving Cache Hits On Replacment Blocks Using Weighted LRU-LFU Combinations

“…To assess the suggested block selection strategy, we simulate single-core and multi-core systems with two-level cache memory subsystems. According to experimental findings, using the memory block selection scheme can increase the hit ratio by up to 11% while reducing overall power usage by up to 20% [16]. In 2016, Somayeh Sardashti studied "Yet Another Compressed Cache: A Low-Cost Yet Effective Compressed Cache" to increase cache memory's adequate capacity.…”