An efficient Modified Booth multiplier architecture

Hussin, Razaidi; Shakaff, Ali Yeon Md; Idris, Norina; Sauli, Zaliman; Ismail, Rizalafande Che; Kamarudin, A.

doi:10.1109/iced.2008.4786767

Cited by 26 publications

(20 citation statements)

References 9 publications

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“…There are different designs of 4-to-2 compressor cells which have been proposed in various literature [10,12,[22][23][24][25]. In this section, several CMOS and CNFET-based 4-to-2 compressor cells are briefly reviewed.…”

Section: Relted Workmentioning

confidence: 99%

“…(13) In the following, the proposed structure is discussed in detail. Fig.2. (a) CMOS design [10], (b) CMOS design [24], (c) CMOS design [22], (d) CMOS design [23], (e) CMOS design [12], ( f) CNFET design [25].…”

Section: Proposed 4-to-2 Compressor Cellmentioning

confidence: 99%

“…In the simulation, CMOS design of [10] Fig.2a, CMOS design of [24] Fig.2b, CMOS design of [22] Fig.2c, CMOS design of [23] Fig.2d, CMOS design of [12] Fig.2e, CNFET design of [25] Fig.2f, and the proposed design, Fig.6, in MOSFET technology are surveyed. Results of this simulation is shown in Table 1.…”

Section: New 4-to-2 Compressor Design Based On Cnfet Bridge Structurementioning

confidence: 99%

“…Design [23] Design [24] Design [22] Design [12] Design [10] Design [25] Porposed In particular, the delay, power consumption, and PDP plotted in Fig.8 in 0.5V, 0.65V, 0.9V, 1.1V, and 1.5V power supply in order to achieve lowest delay, power consumption, and PDP [10].…”

Section: A Temperature Analysismentioning

confidence: 99%

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A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

Darvishi¹,

Bagherizadeh²

2017

IJMECS

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Abstract-In this paper, a new high-speed and energy efficient 4-to-2 compressor cell was presented using carbon nanotube field effect transistors (CNFETs). CNFET is very suitable for high-frequency and lowvoltage applications. In addition, in this paper several conventional and state-of-the-art 4-to-2 compressor cells are surveyed and compared. In order to evaluate the proposed designs, computer simulations are carried out using 32nm-CMOS and 32nm-CNFET technologies. Simulations are conducted using various low voltage power supplies, different temperatures, frequencies and load capacitors. Results of simulation demonstrate predominance of the proposed design in terms of power consumption, delay, and power-delay product (PDP) compared to other 4-to-2 compressor cells and they confirm that the proposed design is the fastest 4-to-2 compressor in various working circumstances.

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Section: Relted Workmentioning

confidence: 99%

Section: Proposed 4-to-2 Compressor Cellmentioning

confidence: 99%

Section: New 4-to-2 Compressor Design Based On Cnfet Bridge Structurementioning

confidence: 99%

Section: A Temperature Analysismentioning

confidence: 99%

See 2 more Smart Citations

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

Darvishi¹,

Bagherizadeh²

2017

IJMECS

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“…First, the multiplicand and multiplier are multiplied to generate partial products. Then, 4:2 or 7:3 compressor units are used to reduce the delay of partial production [5][6][7]. Finally, the final addition is done by Binary-to-Excess-one converter (BEC).…”

Section: Introductionmentioning

confidence: 99%

Speed and area analysis on hierarchy multiplier

Wong

Hussin

2017

EPJ Web Conf.

Self Cite

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Abstract. This paper proposes designs of hierarchy multiplier by utilising different designs on 4:2 and 7:3 compressor and multiple compressors. The hierarchy multipliers is optimised in the term of speed or area of hierarchy multiplier by redesigning 4:2 compressor units and introducing a combination of 4:2 compressor and 7:3 compressor units in a Vedic multiplier block. All designs are simulated using Altera Quartus II software. The aim of this paper is to improve the performance in speed by moderately increasing the area without considering the power consumption. The proposed design is 4.5% to 8.3% faster and consumes -0.5% to 5.8% less area.

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TMA: Tera‐MACs/W neural hardware inference accelerator with a multiplier‐less massive parallel processor

Park

Kim

2021

Circuit Theory & Apps

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Summary Computationally intensive inference tasks of deep neural networks have brought about a revolution in accelerator architecture, aiming to reduce power consumption as well as latency. The key figure‐of‐merit in hardware inference accelerators is the number of multiply‐and‐accumulation operations per watt (MACs/W); the state‐of‐ the‐art MACs/W, so far, has been several hundreds Giga‐MACs/W. We propose a Tera‐ MACS/W neural hardware inference accelerator (TMA) with 8‐bit activations and scalable integer weights less than 1‐byte. The architecture's main feature is a configurable neural processing element for matrix‐vector operations. The proposed neural processing element uses a multiplier‐less massive parallel processor that works without multipliers, which makes it attractive for energy efficient high‐performance neural network applications. We benchmark our system's latency, power, and performance using Alexnet trained on ImageNet. Finally, we compared our accelerator's throughput and power consumption to that of the prior works. The proposed accelerator outperforms the state‐of‐the‐art counterparts, in terms of the energy and area efficiency, achieving 2.3 TMACs/W@1.0 V on a 28‐nm Virtex‐7 FPGA chip.

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An efficient Modified Booth multiplier architecture

Cited by 26 publications

References 9 publications

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

A New High-Performance Bridge Structure for 4- to-2 Compressor using CMOS and CNFET Technology

Speed and area analysis on hierarchy multiplier

TMA: Tera‐MACs/W neural hardware inference accelerator with a multiplier‐less massive parallel processor

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