An efficient network on chip design flow

Abstract

As technology scales and VLSI systems become more and more complex, both bus and crossbar-based architectures are no longer suitable for implementing communications between the system components. Thus, a specific NoC is needed so as to meet the user-defined constraints (area, bandwidth, energy dissipation) while ensuring system reliability. The NoC design flow which is presented in [1] addresses related research problems and includes solutions to cope with them. In this paper, we present a quite different NoC design flow that targets the following features: i) the NoC is customized and distributed; ii) the generated NoC architecture is dedicated to design either real-time systems or high-throughput ones while meeting the area and power dissipation constraints; iii) the system reliability problem is addressed.International Technology Roadmap for Semiconductors (ITRS) shows that interconnect design is one of the main issues which are encountered for designing VLSI systems in new CMOS technologies. Although the gate delay is more and more enhanced (because the transistor channel is more and more reduced), parasitic capacitance values grow as technology scales. Indeed, it is shown in [2] that the parallel capacitance is 6 and 8 times greater than the wire one in 0.35 flm and 0.18 flm CMOS technology, respectively. Because such parasitic capacitances have a negative impact on throughput and power dissipation [27], solutions to cope with this problem need to be provided. In 2000, IBM replaced aluminum with copper, somewhat enhancing the interconnect delay (thanks to reducing both capacitance and resistance of the wire). Other solutions have been adopted at design level (e.g. buffer insertion technique to reduce the wire capacitance or data encoding to reduce the parallel capacitances) but the problem is still arising (the interconnect delay is still increasing as technology scales). In parallel with technology scaling, the new systems become more and more complex while featuring high communication degree. Integrating such systems on the same SoC makes both bus and crossbar-based architectures unsuitable because of the limited bandwidth, contention, etc.. Thus, one needs to 978-1-4673-7005-9 /15/$31.00 ©2015 IEEE design a specific NoC that meets the user-constraints (e.g. bandwidth, area, power dissipation) while ensuring system reliability. Many works have been achieved in this area and are mainly based on mesh, fat trees and their variant topologies. Concerning the fat trees (and their variants) topologies, they feature a dense network that yields many parasitics, which is detrimental to both throughput and power dissipation. Mesh networks (and their variants) are intensively used as topologies for designing aNoC. Because such topologies need a switch library, the problem arises when a specific switch (e.g. 5x9) does not exist in the library (such library could not contain all the needed instances): this could be detrimental for area, throughput and power dissipation since those missing switches should be replaced w...