An Efficient Numerical Solution Technique for VLSI Interconnect Equations on Many-Core Processors

Abstract

This paper presents a technique to accelerate transient simulations of analog circuits using an explicit integration method parallelised on a many-core computer. Usual methods used by SPICE-type simulators are based on Newton-Raphson iterations, which are reliable and numerically stable, but require long CPU processing times. However, although the integration time step in explicit methods is smaller than that used in implicit methods, this technique avoids the calculation of time-consuming computations due to the Jacobian matrix inversion. The proposed method uses an explicit integration scheme based on the fourth order Adams-Bashforth formula. The algorithm has been parallelised on a NVIDIA general purpose GPU using the CUDA programming model. As a case study, the RC ladder model of a VLSI interconnect is simulated on a general purpose graphic processing unit and the achieved performance is then evaluated against that of a multiprocessor CPU. The results show that the proposed technique achieves a speedup of one order of magnitude in comparison with implicit integration techniques executed on a CPU.

High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processors

“…The simulation technique described in previous section has been applied to simulate the system described in equations (10) to (12). To test the speedup of the proposed method, several transient simulations of 1µs each have been run for CMOS imagers of different sizes.…”

“…Given that the calculation of ||J|| is computationally expensive, an alternative method to estimate the maximum step size is presented in [3]. However, this method is valid for definite negative matrices, as shown in [12], a condition which is not always accomplished. Thus, in this work the following estimation is proposed.…”

Stability and Efficiency of Explicit Integration in Interconnect Analysis on GPUs

“…3 describes the procedure to compute the values of the state variables on a general purpose. Compared to the fixed step implementation [15], the proposed variable step algorithm presents the following differences. First, there are two calls to GPU parallel execution in each time step.…”

“…A common characteristic of these works is that they are still focused on the traditional implicit integration methods used for simulators like SPICE. Recently, an explicit integration method parallelizable over a many-core processors has been proposed [15]. This method combines space state equations with a fixed-step explicit schema to speedups the simulation of passive circuits of a complexity up to 1000 nodes.…”