An efficient reconfiguration scheme for fault-tolerant meshes

Chuang, Po‐Jen; Yao, Li-Chiang

doi:10.1016/j.ins.2004.05.003

Cited by 17 publications

(9 citation statements)

References 23 publications

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“…Using the same assumptions as in [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34], [35], [36], [37], [38], [39], [40], [41], [42], [43], all switches and interconnects in an array are assumed to be fault-free. This assumption is justified since the switches and links use much less hardware resources when compared to the PEs and are thus less vulnerable to faults.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…Reported approaches on the switch-based architecture can be classified into two categories, i.e., the redundancy approach [24], [25], [26], [27] and the degradation approach. The former replaces faulty PEs using spare ones to obtain a logical array with a guaranteed size, while the latter tries to provide a target array as large as possible.…”

Section: Introductionmentioning

confidence: 99%

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Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

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With the increased density of three-dimensional (3D) processor arrays, faults can potentially occur quite often due to power overheating during massively parallel computing. In order to achieve fault-tolerance under such a scenario, an effective way is to find an as large as possible logical fault-free subarray of m 0 Â n 0 Â h 0 from a faulty array of m Â n Â h (m 0 m; n 0 n; h 0 h), such that an original application can still work on the m 0 Â n 0 Â h 0 subarray. This paper investigates the problem of constructing maximum fault-free subarrays with minimum interconnection length from 3D arrays with faults. First, we prove that constructing maximum logical array (MLA) is NP-complete. We propose a linear-time algorithm which is capable of producing an MLA for the problem with the constraint of selected indexes. Second, we prove that minimizing the interconnection length (inter-length) of the MLA is NP-hard. We propose an efficient heuristic which significantly reduces the inter-length by revising each logical plane of the MLA. This leads to the reduction of communication cost, capacitance and dynamic power dissipation. In addition, we propose a lower bound for the inter-length of the MLA to evaluate the proposed algorithms. Simulation results show that, the size of logical array can be improved up to 62.6 percent in average, and the inter-length redundancy can be reduced by 22.7 percent in average, compared to the state-of-the-art, for all cases considered.Index Terms-3D processor array, fault tolerance, maximum logical array, interconnection length, NP-complete problem, algorithm Ç G. Jiang is with the

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Jiang

et al. 2015

IEEE Trans. Comput.

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“…For a mesh‐connected processor array, numerous studies on fault tolerance have been undertaken in recent years, primarily focusing on two methods for fault‐tolerant techniques, namely the redundancy approach and the degradation approach. In the redundancy approach, a system is constructed to include several spare PEs, which are utilized to replace faulty PEs in the reconfigurable system . The main drawback of this approach is that, if the number of spare PEs is insufficient to replace all the faulty PEs, then the system cannot be reconfigured and must be discarded.…”

Section: Introductionmentioning

confidence: 99%

Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays

Qian

Bai

Zhou

et al. 2017

IEEJ Transactions Elec Engng

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Employment of fault‐tolerant techniques is necessary for the operability and reliability of very large scale integration (VLSI) arrays. Moreover, fault tolerance must be obtained at high speed on real‐time embedded systems. In this paper, a novel abstract model, based on the abstraction technique, is proposed to accelerate the reconfiguration of degradable VLSI arrays with low fault density. Given an m × n physical array with faults, the proposed technique extracts some physical rows including faulty elements to construct an abstraction array, ignoring the physical rows without faults, such that the size of original physical array can be significantly reduced to speed up the reconfiguration of VLSI array. In addition, we conclusively demonstrate the preservation of properties between the abstract array and the physical array to guarantee that the proposed technique is correct. Experimental results show that for a 128 × 128 physical array with 0.1% faults, a 15 × 128 abstract array can be constructed and the compression is more than 88.20%. This abstraction technique is bound into a reconfiguration algorithm cited in this paper. Simulation results show that the running time can be improved by more than 66.79% for a 128 × 128 physical array with 0.1% faults. © 2017 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.

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“…In the redundancy approach, the system is built with some spare PEs, which are used to directly replace the faulty PEs in the reconfigurable system. Varieties of techniques are described in the literatures to restructure a faulty physical system into a faultfree target logical system with spare rows and columns [1,2]. However, the main drawback of this approach is the fixed size of a reconfigured array; that is, the system cannot be reconfigured and has to be discarded if the spare PEs cannot replace all the faulty PEs.…”

Section: Introductionmentioning

confidence: 99%

Satisfiability-based method for reconfiguring power efficient VLSI array

Qian

Cao

et al. 2016

IEICE Electron. Express

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Fault-tolerant techniques are absolutely vital for large scale multiprocessor array as it suffers from frequent hardware defects or soft faults. This paper presents a satisfiability (SAT)-Based method for the reconfiguration of a two-dimensional degradable very-large-scale integration (VLSI) array with faulty processing elements (PEs). An SAT model of the target array is proposed such that the target array can be constructed by using the efficient SAT solver. For minimizing the interconnection length of the target array, we present an incomplete algorithm, to search a target array with suitable interconnection length to meet the system requirement. Our evaluations show that the proposed incomplete algorithm is efficient, which is compared with the state-of-the-art.

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An efficient reconfiguration scheme for fault-tolerant meshes

Cited by 17 publications

References 23 publications

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Reconfiguring Three-Dimensional Processor Arrays for Fault-Tolerance: Hardness and Heuristic Algorithms

Efficient abstraction algorithms for accelerating reconfiguration of VLSI arrays

Satisfiability-based method for reconfiguring power efficient VLSI array

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