An efficient retiming algorithm under setup and hold constraints

Abstract

Among these researches, many were focus on minimizing clock In this paper we present a new efficient algorithm for retiming se-period [1,8,[11][12][13]24,27,28]. However, the polynomial-time retimquential circuits with edge-triggered registers under both setup and ing algorithms proposed in these papers can only be used to satisfy hold constraints. Compared with the previous work [17], which setup constraint. computed the minimum clock period in O(lVl3 JEl lg IV() time, our An algorithm was presented in [22] for retiming single-phase algorithm solves the same problem in (IV12El) time. Experimen-level-clocked circuits under both setup and hold constraints, but tal results validate the efficiency of our algorithm. its worst-case running time was exponential. On the other hand, [23] proposed to handle hold constraint by inserting extra delays on Categories and Sub ect Descriptors short paths, but it may result in significant area penalty and may fail Categories and Subject Descriptors when the delay insertion is required to be discrete. The existence B.7.2 [Hardware]: Integrated Circuits-Design Aids; of a polynomial-time algorithm for minimum period retiming of J.6 [Computer-Aided Engineering]: Computer-Aided Design edge-triggered circuits under both setup and hold constraints has remained as an open problem until [17]. General Terms Given an edge-triggered sequential circuit G= (V, E), a target clock period, a setup time S, and a hold time H, the algorithm Algorithms, Performance, Design in [17] computed a valid retiming satisfying both setup and hold constraints, or reported that there is no such a retiming. However, Keywords its worst-case running time was high. In conjunction with binary search, it took O(jV13JEllglVl) time to determine the minimum clock period.In this paper we present an algorithm that finds a minimum pe-