An Efficient Selection-Based kNN Architecture for Smart Embedded Hardware Accelerators

Abstract

K-Nearest Neighbor (kNN) is an efficient algorithm used in many applications e.g. text categorization, data mining, and predictive analysis. Despite having a high computational complexity, kNN is a candidate for hardware acceleration since it is a parallelizable algorithm. This paper presents an efficient novel architecture and implementation for a kNN hardware accelerator targeting modern System-on-Chips (SoCs). The architecture adopts a selection-based sorter dedicated for kNN that outperforms traditional sorters in terms of hardware resources, time latency, and energy efficiency. The kNN architecture has been designed using High-Level Synthesis (HLS) and implemented on the Xilinx Zynqberry platform. Compared to similar state-of-the-art implementations, the proposed kNN provides speedups between 1.4× and 875× with 41% to 94% reductions in energy consumption. To further enhance the proposed architecture, algorithmic-level Approximate Computing Techniques (ACTs) have been applied. The proposed approximate kNN implementation accelerates the classification process by 2.3× with an average reduced area size of 56% for a real-time tactile data processing case study. The approximate kNN consumes 69% less energy with an accuracy loss of less than 3% when compared to the proposed Exact kNN.

From a Chemotherapeutic Drug to a High-Performance Nanocatalyst: A Fast Colorimetric Test for Cisplatin Detection at ppb Level

“…Hence, with the aim of combining accurate quantitative analyses with POC characteristics for fast on-site screenings, we designed and developed a quantitative approach relying on machine-learning (ML) methods, working with very basic video cameras (thus being also suitable for application with standard smartphones). In particular, our ML approach exploited the kinetic information of the colorimetric reaction and a combination of dynamic time warping (DTW) [ 59 , 60 , 61 , 62 ] with the K-nearest neighbors (KNN) algorithm [ 63 , 64 , 65 ], allowing the use of a very limited experimental dataset. The details of the ML procedure are reported in Supporting Information and Materials and Methods .…”

Efficient Hardware Accelerators for k-Nearest Neighbors Classification using Most Significant Digit First Arithmetic

“…Ref. [Youn21] addresses the challenges of efficiently implementing the k-NN algorithm on modern heterogeneous System-on-Chips (SoCs) with specialized hardware. It proposes a novel selection-based sorter for k-NN that reduces hardware area by up to 48% while achieving a speedup of up to 4.5×.…”

“…While each platform has pros and cons, FPGA, by providing an acceptable trade-off, offers programmability and flexibility of processors besides the considerable performance and low power consumption of ASICs [Said21]. Therefore, it has attracted the attention of many researchers that leverage FPGA features to address various computation-intensive machine learning applications [Duar19], [Tara20], and also k-NN algorithm [Youn21].…”