An Efficient Technique for Hardware/Software Partitioning Process in Codesign

Mhadhbi, Imene; Othman, Slim Ben; Saoud, Slim Ben

doi:10.1155/2016/6382765

Cited by 11 publications

(8 citation statements)

References 22 publications

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“…While system profilers can assist in providing an insight about the system's behavior and help identify the parts of the code that can be accelerated on hardware, partitioning should be an automatic process and requires no external involvement. There are several algorithms proposed to address the challenges of partitioning, such as PSO, FCM, and FCMPSO [193]. These are optimization algorithms used to mapping embedded applications to Directed Acyclic Graphs (DAGs) for multi-core architectures.…”

Section: E Co-designmentioning

confidence: 99%

Software-defined Radios: Architecture, state-of-the-art, and challenges

Akeela

Dezfouli

2018

Computer Communications

114

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Software-defined Radio (SDR) is a programmable transceiver with the capability of operating various wireless communication protocols without the need to change or update the hardware. Progress in the SDR field has led to the escalation of protocol development and a wide spectrum of applications, with more emphasis on programmability, flexibility, portability, and energy efficiency, in cellular, WiFi, and M2M communication. Consequently, SDR has earned a lot of attention and is of great significance to both academia and industry. SDR designers intend to simplify the realization of communication protocols while enabling researchers to experiment with prototypes on deployed networks. This paper is a survey of the state-of-theart SDR platforms in the context of wireless communication protocols. We offer an overview of SDR architecture and its basic components, then discuss the significant design trends and development tools. In addition, we highlight key contrasts between SDR architectures with regards to energy, computing power, and area, based on a set of metrics. We also review existing SDR platforms and present an analytical comparison as a guide to developers. Finally, we recognize a few of the related research topics and summarize potential solutions.

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Section: E Co-designmentioning

confidence: 99%

Software-defined Radios: Architecture, state-of-the-art, and challenges

Akeela

Dezfouli

2018

Computer Communications

114

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“…However, embedded system Bulletin of Electr Eng & Inf ISSN: 2302-9285  design has increased in complexity over the years, making manual partitioning tedious because of the large number of components with different characteristics that must be considered [2][3][4][5][6][7][8][9]. Therefore, many researches have been conducted to implement the hardware software partitioning automatically [10][11][12][13][14][15]. The hardware software partitioning can be categorized as exact algorithm and heuristic algorithm.…”

Section: Introductionmentioning

confidence: 99%

Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

et al. 2021

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This study discusses hardware-software partitioning, which is useful for system-on-chip (SoC) applications. Hardware-software partitioning attempts to obtain the lowest execution time by combining a hardware processor system and a field programmable gate array on the SoC platform in embedded system applications. A three-level hybrid algorithm called GAGAPSO is proposed in this study. The algorithm consists of two successive genetic algorithms (GAs) and one particle swarm optimization (PSO). The drawbacks of these two algorithms are GA has low convergence speed and PSO has premature convergence because of low diversity. These algorithms are combined in this study to achieve high-capacity global convergence and enhanced search efficiency. In this study, three algorithms are developed, namely, GA, GAPSO and GAGAPSO using MATLAB. These algorithms are evaluated on the basis of the number of nodes and the minimum cost that can be achieved. The number of nodes varies from 10 to 1000 nodes. The minimum cost and the number of iterations to achieve the minimum cost are recorded. Results show that GAGAPSO can converge faster than GA and GAPSO. Furthermore, GAGAPSO can achieve the lowest cost for all nodes.

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“…Efficient techniques for HW/SW co-design [9]- [11] are necessary to realize embedded systems that must meet design constraints while satisfying the shorter time-to-market pressures [12]. HW/SW partitioning [9], [13], [14] is the crucial step during HW/SW co-design, and the HW/SW partitioning algorithm determines which components are implemented in hardware and which components are implemented in software [15]. First, it can guide the design and configuration of computing resources, reducing the overall power to achieve regional optimization; second, the system can be optimized to obtain the maximum acceleration.…”

Section: Introductionmentioning

confidence: 99%

“…By performing a small number of tasks in parallel, it combines other overhead costs (communication and memory I/O) analysis to benefit or not. In recent years, much research has been performed on HW/SW partitioning, which can be divided into structure partitioning and functional partitioning [13], [17], [18]. Structure partitioning has more blocks, usually using functional partitioning.…”

Section: Introductionmentioning

confidence: 99%

A Memory-Reinforced Tabu Search Algorithm With Critical Path Awareness for HW/SW Partitioning on Reconfigurable MPSoCs

Guo¹,

Zhang²,

Zhao³

2019

IEEE Access

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Hardware/software (HW/SW) partitioning and scheduling are the crucial steps in HW/SW co-design. They have a strong effect on performance, area, power and the system itself. In this paper, a memory-reinforced tabu search algorithm with critical path awareness (MTSP) is proposed for solving the HW/SW partitioning problem. First, the critical path (CP) algorithm can locate the critical task queues and output a reduced task graph. Second, the solution to a heuristic algorithm (HA) is used as the initial solution. Third, by introducing hash technology, adding dual memory tables improves the search strength and effectiveness of the tabu search, and the experiment is completed by priority scheduling. MTSP especially has good performance in large task graphs, while it can greatly improve system performance, especially in the case of generating a large communication penalty. The experimental results show that the average improvement over the latest efficient hybrid algorithm is up to 5%. The improvement in algorithm searching time is 66% in comparison to the popular algorithms cited in this paper. INDEX TERMS Hardware/software partitioning, task graph, heuristic method, tabu search algorithm, MPSoC.

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An Efficient Technique for Hardware/Software Partitioning Process in Codesign

Cited by 11 publications

References 22 publications

Software-defined Radios: Architecture, state-of-the-art, and challenges

Software-defined Radios: Architecture, state-of-the-art, and challenges

Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

A Memory-Reinforced Tabu Search Algorithm With Critical Path Awareness for HW/SW Partitioning on Reconfigurable MPSoCs

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