An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition

Nandan, Durgesh; Kanungo, Jitendra; Mahajan, Anurag

doi:10.1016/j.vlsi.2017.02.003

Cited by 22 publications

(5 citation statements)

References 22 publications

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“…In 2016, Juang et al have given two-region antilogarithm approximation ranges -0.60 to 1.72 and ranges over 2.3232 for antilogarithm converter [31]. Durgesh Nandan et al have suggested efficient hardware at the same error cost in comparison of reported design in 2016 and 2017, [8,32]. Kuo [34].…”

Section: Systematic Growth Of Literaturementioning

confidence: 99%

“…Many handheld and portable signal-processing devices are parts of our daily life. The Digital signal processor and image processor have required accurate and efficient arithmetic operations for performing fast and efficient real-time applications [1][2][3][4][5][6][7][8][9]. As its well-known thing, that multiplier is the most utilized component in arithmetic operations.…”

Section: Introductionmentioning

confidence: 99%

“…As its well-known thing, that multiplier is the most utilized component in arithmetic operations. Many researchers' efforts have been directed to develop an accurate and efficient multiplier design [6][7][8][9][10][11][12][13]. Nowadays filters applications required an efficient multiplier design.…”

Section: Introductionmentioning

confidence: 99%

“…Logarithm multiplication operation can be performing in three steps: (1) Conversion of any format numbers into logarithmic numbers, (2) then performed addition on logarithmic numbers, and then (3) convert back into initial format numbers [8]. The pictorial representation of logarithm multiplication is shown in Figure 1.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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Digital Signal Processing (DSP) applications demand error-free and compact hardware architecture of arithmetic operations. A logarithmic operation provides an efficient option in place of binary arithmetic. In this paper, it is suggested that 11-region and 17-region error correction schemes for developing an efficient antilogarithm converter. It is used for developing the most accurate and compact logarithm multiplier which is used in the DSP processor. Implementations of reported and proposed designs are investigate based on accuracy and hardware overhead and it found outperform in comparisons of previously reported designs. The proposed 11-region converter involves 61% less Area Delay Product (ADP) and 49.82% less energy in comparisons of the reported 11-region antilogarithmic converter and 17-region converter involves 48.02% less ADP and 32.53% less energy in comparisons of the reported 14-region antilogarithmic converter. The proposed antilogarithmic converter achieves 1.697% and 1.084% error for 11-region and 17-region designs respectively than of reported designs of 1.876% and 1.351% for 11-region and 17region respectively.

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Section: Systematic Growth Of Literaturementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Nandan¹

2020

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“…Design of LOD is important as they are used for the normalization process in floating point multiplication, logarithmic multiplication and in logarithmic converters [12][13][14][15][16][17]. In this paper, we have designed the novel reversible LOD.…”

Section: Introductionmentioning

confidence: 99%

Implementation of Leading One Detector based on Reversible Logic for Logarithmic Arithmetic

Nandan¹,

Kanungo²,

Mahajan³

2017

IJCA

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Nowadays computers are more efficient and more complex than their predecessors. But, there is some penalty of each and every advantage in the field of technology. Here, penalty comes in terms of power consumption. According to Moore's law, primary reasons for the rise in power consumption are the increase in clock frequency and the increased number of transistors packed onto in same die area. Reversible logic provides high speed and less power consumption. So, it has been widely used in designing of digital circuits for lowpower and high-speed computation. Design of Leading One Detector (LOD) is an important circuit as they are used for the normalization process in floating point multiplication, logarithmic multiplication, and in logarithmic converters as useful components. In this paper, we designed a novel LOD based on reversible logic. In order to construct leading-one detector, the innovative reversible Feynman gate (FG) and a special case of TKS gate are proposed. The 4-bit, 8-bit, 16-bit and 32-bit LOD are designed based on the above blocks and some existing reversible gates. VHDL programmed for LOD have been modeled. According to the simulation results, our circuit's logic structures are validated. In terms of Ancillary inputs, garbage outputs quantum cost and delay are compared with the reported works. It can be concluded that our designs perform better than the others. There is no doubt that these can be used as an important component the upcoming lowpower quantum computing systems.

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The Hardware Design Prospective of Object Detection by Using Background Subtraction Techniques: An Analytical Review

Kumar

Nandan

Mishra

2020

Advances in Intelligent Systems and Computing

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An efficient VLSI architecture design for logarithmic multiplication by using the improved operand decomposition

Cited by 22 publications

References 22 publications

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

An Efficient Antilogarithmic Converter by Using Correction Scheme for DSP Processor

Implementation of Leading One Detector based on Reversible Logic for Logarithmic Arithmetic

The Hardware Design Prospective of Object Detection by Using Background Subtraction Techniques: An Analytical Review

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