An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Zhang, Wei; Jiang, Zhe; Gao, Zhiyu; Liu, Yanyan

doi:10.1109/tcsii.2012.2184369

Cited by 69 publications

(91 citation statements)

References 18 publications

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“…The biorthogonal two dimensional discrete wavelet transform structure is computed in row-column manner. [23][24][25][26].The image stored in the external memory is read to the processing core in a row wise order. The horizontal filtering are done to the rows that consists of the computing modules as per the lifting scheme.…”

Section: Lifting Based Dwtarchitecturementioning

confidence: 99%

Implementation of DWT Integrated Log Based FPU with SPIHT Coders on FPGA

N.RamyaRani¹

2016

IJAERS

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Section: Lifting Based Dwtarchitecturementioning

confidence: 99%

Implementation of DWT Integrated Log Based FPU with SPIHT Coders on FPGA

N.RamyaRani¹

2016

IJAERS

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“…Booth recoding is a technique for high speed multiplication, by recoding the bits that are multiplied. The number of partial products reduced to half, using the technique of radix-4 Booth recoding [1], [2][6].…”

Section: Radix-4 Booth Multipliermentioning

confidence: 99%

“…Half adder is used to generate sum and carry in CSA. The generated carry is stored in accumulator [1][11].…”

Section: Architecture Of a Multipliermentioning

confidence: 99%

“…Adopted by the JPEG 2000 image compression standard [1], it significantly outperforms algorithms based on other transforms, such as the discrete cosine transform, in terms of objective metrics as well as perceptual image quality [2]. The success of the DWT stems from its ease of computation and its inherent decomposition of an image into non-overlapping subbands that enables the design of efficient quantization algorithms and allows for incorporation of the human visual system.…”

Section: Introduction To Dwtmentioning

confidence: 99%

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Simulation Analysis of 2-D Discrete Wavelet Transform by using Modified Radix-4 Booth Multiplier

Nikhare¹,

Singhadia²

2015

International Journal of Advanced Research in Computer and Comm

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Abstract:A new architecture namely 2-D DWT, Multiplier-and accumulator (MAC) based Radix-4 Booth Multiplication Algorithm for high-speed arithmetic logics have been proposed and implemented on Xilinx. By combining multiplication with accumulation and devising a hybrid type adder the performance was improved. The modified booth encoder will reduce the number of partial products generated by a factor of 2. Fast multipliers are essential parts of digital signal processing systems. The speed of multiply operation is of great importance in digital signal processing as well as in the general purpose processors. The number to be added is the multiplicand, the number of times that it is added is the multiplier, and the result is the product. Each step of addition generates a partial product. the simulation is done on the Modelsim and finally output is analysed by using Matlab.

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“…But critical path reduction is always obtained at the cost of increase in latency and number of registers. The papers that have worked on critical path minimization are [18], [19]. The implementation of most of these architectures is based on FPGA using VHDL synthesis, however MATLAB/Simulink/Xilinx System Generator can also be utilized for the same [20], which helps portability and rapid time-to-market of the architecture.…”

Section: Introductionmentioning

confidence: 99%

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

Lone

ud-Din

2017

IJATES

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Abstract-For real-time applications, efficient VLSI implementation of DWT is desired. In this paper, DWT architecture based on retiming for pipelining and unfolding is presented. The architecture is based on lifting one-dimensional CohenDaubechies-Feauveau (CDF) (5,3) wavelet filter, which is easily extended to 2-D implementation. It consists of low complexity and easily repeatable components. This paper is focused on the critical path minimization and throughput optimization at the same time. The architecture has been implemented on Virtex 6 Xilinx FPGA platform. The implementation results show that the critical path is minimized four to five times, while throughput is doubled, making the overall architecture approximately ten times faster when compared with the conventional lifting-based DWT architecture. Further with parallel implementation, the throughput has doubled without any increase in number of row buffers, implying that the architecture is memory efficient as well. The even and odd rows of the image are scanned in parallel fashion. To perform the 2-D DWT transform of an image of size 15 Megapixels, it takes 16.86 ms, which implies 59 images of that size can be processed in one second. This can be utilized for real-time video processing applications even for high resolution videos.

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An Efficient VLSI Architecture for Lifting-Based Discrete Wavelet Transform

Cited by 69 publications

References 18 publications

Implementation of DWT Integrated Log Based FPU with SPIHT Coders on FPGA

Implementation of DWT Integrated Log Based FPU with SPIHT Coders on FPGA

Simulation Analysis of 2-D Discrete Wavelet Transform by using Modified Radix-4 Booth Multiplier

A High Speed Architecture for Lifting-based 2-D Cohen-Daubechies-Feauveau (5,3) Discrete Wavelet Transform used in JPEG2000

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