2015 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA) 2015
DOI: 10.1109/apsipa.2015.7415359
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An efficient VLSI architecture for discrete wavelet transform

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Cited by 3 publications
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“…Even though it reduced the power the architecture is more complex with larger area occupation on FPGA. An interlacing coding is suggested for the image interfacing in SVC is outlined in [2]. A brief outline to image coding using SVC and AVC interlacing is suggested.…”
Section: Related Workmentioning
confidence: 99%
“…Even though it reduced the power the architecture is more complex with larger area occupation on FPGA. An interlacing coding is suggested for the image interfacing in SVC is outlined in [2]. A brief outline to image coding using SVC and AVC interlacing is suggested.…”
Section: Related Workmentioning
confidence: 99%