An Embedded Processor Based SOC Test Platform

Abstract

In this paper we present a novel test platform for embedded processor based system-on-a-chip (SoC). The embedded processor is employed as a control kernel to execute the test programs for all the cores in the SoC. A dedicated Test Access Mechanism (TAM) controller is developed which controls the actual test procedure for each core such that no extra buffer is needed for individual cores. The TAM controller together with the test programs can execute scan-based testing, memory BIST and mixed-signal BIST. The platform can test cores wrapped by the standard boundary scan and the IEEE P1500 wrappers, as well as hierarchical and mixed-signal cores. Our methodology alleviates the need of expensive automatic test equipment (ATE), and hence can greatly reduce the total test cost. Experimental results show the effectiveness of the proposed test platform.I.

Towards an automated and reusable in-field self-test solution for MPSoCs

“…The TAM could be the same as the functional network [5], in this case both the LBIST test data and the functional data share the same network bandwidth which may lead to network congestion. A dedicated TAM could also be used [7] at the cost of silicon area and routing.…”