An Embedded Reconfigurable Datapath for SoC

Lodi, Andrea; Ciccarelli, L.; Mucci, Claudio; Giansante, Roberto; Cappelli, Andrea

doi:10.1109/fccm.2005.18

Cited by 4 publications

(2 citation statements)

References 3 publications

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“…CGRAs embedded in SoCs [Lodi et al 2005;Khawam et al 2003] present new opportunities for further customization for target applications. In today's design processes, many soft cores integrated into an SoC go through a configuration step before the SoC is optimized for various design objectives.…”

Section: Introductionmentioning

confidence: 99%

Architecture customization of on-chip reconfigurable accelerators

Yoon

Lee

Park

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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Integrating coarse-grained reconfigurable architectures (CGRAs) into a System-on-a-Chip (SoC) presents many benefits as well as important challenges. One of the challenges is how to customize the architecture for the target applications efficiently and effectively without performing explicit design space exploration. In this article we present a novel methodology for incremental interconnect customization of CGRAs that can suggest a new interconnection architecture which is able to maximize the performance for a given set of application kernels while minimizing the hardware cost. In our methodology, we translate the problem of interconnect customization into that of inexact graph matching, and we devised a heuristic for A* search algorithm to efficiently solve the inexact graph matching problem. Our experimental results demonstrate that our customization method can quickly find application-optimized interconnections that exhibit 80% higher performance on average compared to the base architecture which has mesh interconnections, with little energy and hardware increase in interconnections and muxes.

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Section: Introductionmentioning

confidence: 99%

Architecture customization of on-chip reconfigurable accelerators

Yoon

Lee

Park

et al. 2013

ACM Trans. Des. Autom. Electron. Syst.

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“…PiCoGA [1] and PACT XPP [2]), numerous commercial ventures (e.g. Nethra/Ambric, Tilera, Picochip, IntellaSys) have begun producing such devices.…”

Section: Introductionmentioning

confidence: 99%

Self-hosted placement for massively parallel processor arrays

Smecher

Wilton

Lemieux

2009

2009 International Conference on Field-Programmable Technology

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Abstract-We consider the placement problem as part of the CAD flow for a massively parallel processor arrays (MPPAs). In contrast to traditional placers, which operate on a workstation with one or several cores and are able to take advantage of parallelism to a limited degree, we investigate running the placer on the target architecture itself. As the number of processor elements (PEs) in such a device scale, so too does the computational power available to the placer. This natural scaling helps avoid the long runtimes that afflict FPGA flows.In this paper, we propose a distributed placer suitable to run on a MPPA. This placer takes advantage of local interconnect fabric, and may be efficiently coded on a simple, RISC-like core. We investigate the performance of this placer and compare it to traditional, simulated annealing-based placers using both unrealistic (but nearly optimal) and realistic (but suboptimal) annealing schedules.On a simulated 32 × 32 = 1024-core MPPA, the proposed algorithm furnishes placements within 5% of the optimal placement quality -a level competetive with the realistic, traditional placer. To do so, the distributed placer requires each PE to consider 1/256 th as many swaps as the traditional placer, a computational advantage which scales favourably as the number of cores on the MPPA increases.

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