An energy conscious methodology for early design exploration of heterogeneous DSPs

Wan, M.; Ichikawa, Yuji; Lidsky, David; Rabaey, Jan M.

doi:10.1109/cicc.1998.694918

Cited by 34 publications

(26 citation statements)

References 9 publications

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“…These approaches, while flexible, have limited scalability due to the arbitrated and capacitive nature of their interconnection. Other notable, common threads through on-chip interconnect architectures include the simplicity of the logic needed on a per node basis to support communication, their diverse support for numerous master/slave interconnection topologies [8], and their integrated support for on-chip testing. Several current on-chip interconnects [3], [7] support the connection of multiple buses in variable topologies (e.g., partial crossbar, tree).…”

Section: Related Workmentioning

confidence: 99%

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An architecture and compiler for scalable on-chip communication

Liang

Laffely²,

Srinivasan

et al. 2004

IEEE Trans. VLSI Syst.

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Abstract-A dramatic increase in single chip capacity has led to a revolution in on-chip integration. Design reuse and ease of implementation have became important aspects of the design process. This paper describes a new scalable single-chip communication architecture for heterogeneous resources, adaptive system-on-a-chip (aSOC) and supporting software for application mapping. This architecture exhibits hardware simplicity and optimized support for compile-time scheduled communication. To illustrate the benefits of the architecture, four high-bandwidth signal processing applications including an MPEG-2 video encoder and a Doppler radar processor have been mapped to a prototype aSOC device using our design mapping technology. Through experimentation it is shown that aSOC communication outperforms a hierarchical bus-based system-on-chip (SoC) approach by up to a factor of five. A VLSI implementation of the communication architecture indicates clock rates of 400 MHz in 0.18-m technology for sustained on-chip communication. In comparison to previously-published results for an MPEG-2 decoder, our on-chip interconnect shows a runtime improvement of over a factor of four.Index Terms-Communications architecture, on-chip interconnect, system-on-chip (SoC).

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Section: Related Workmentioning

confidence: 99%

“…These compilers target bus-based interconnect rather than a point-to-point network. Cost-based tradeoffs between on-chip hardware, software, and communication were evaluated by Wan et al [8]. In Dick and Jha [21], on-chip task partitioning was followed by a hill-climbing based task placement stage.…”

Section: F Comparison To Previous Mapping Toolsmentioning

confidence: 99%

An architecture and compiler for scalable on-chip communication

Liang

Laffely²,

Srinivasan

et al. 2004

IEEE Trans. VLSI Syst.

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“…Hardware/software partitioning has been shown to provide excellent performance as well as power and/or energy improvements compared to software-only implementations in embedded computing systems [4] [29]. Making such partitioning even more attractive is the appearance of single-chip platforms, some of which are intended for consumer products, that include both a microprocessor and configurable logic [1][3] [13] [23][27] [30].…”

Section: Introductionmentioning

confidence: 99%

Codesign-extended applications

Grattan

Stitt

Vahid

2002

Proceedings of the Tenth International Symposium on Hardware/Software Codesign - CODES '02

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We challenge the widespread assumption that an embedded system's functionality can be captured in a single specification and then partitioned among software and custom hardware processors. The specification of some functions in software is very different from the specification of the same function in hardware -too different to conceive of automatically deriving one from the other. We illustrate this concept using a digital camera example. We introduce the idea of codesign-extended applications to deal with the situation, wherein critical functions are written in multiple versions, and integrated such that simple compiler/synthesis flags instantiate a particular version along with the necessary control and communication behavior. By capturing a specification as a codesign-extended application, a designer enables smooth migration among platforms with increasing amounts of on-chip configurable logic. KeywordsHardware/software partitioning, hardware/software cospecification, configurable logic, system-on-a-chip, platformbased design.

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“…1,2 But, because of configurable logic's high power consumption, partitioning that uses configurable logic has mainly targeted speedup. [3][4][5] Energy is the product of power and time, so the power increase from using configurable logic could outweigh the time savings.…”

mentioning

confidence: 99%