An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family

Huang, Min; Mehalel, Moty; Arvapalli, Ramesh; He, Songnian

doi:10.1109/jssc.2013.2258815

Cited by 23 publications

(14 citation statements)

References 2 publications

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“…The SRAM banks were modeled as being similar to that of the Intel R Xeon R E5 processor LLC design [19]. The L2 is modeled as a 2 (wide) ×4 (high) array of 32KB SRAM banks.…”

Section: Methodsmentioning

confidence: 99%

“…A topology similar to Figure 4a was adopted for the design of an LLC slice in the Intel R Xeon R E5 family of processors [19] and a proposed SRAM macro design by Samsung [35]. In such a topology, if the ways of the cache are interleaved across the various SRAM banks, there can be a significant energy difference between the various line locations.…”

Section: Cache Organizationsmentioning

confidence: 99%

“…Different shades are different ways. 4a has non-uniform energy access, adopted by Intel[19] and SRAM macro by Samsung[35]. 4b and 4c have uniform energy access.…”

mentioning

confidence: 99%

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Slip

Das

Aamodt

Dally

2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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Wire energy has become the major contributor to energy in large lower level caches. While wire energy is related to wire latency its costs are exposed differently in the memory hierarchy. We propose Sub-Level Insertion Policy (SLIP), a cache management policy which improves cache energy consumption by increasing the number of accesses from energy efficient locations while simultaneously decreasing intra-level data movement. In SLIP, each cache level is partitioned into several cache sublevels of differing sizes. Then, the recent reuse distance distribution of a line is used to choose an energyoptimized insertion and movement policy for the line. The policy choice is made by a hardware unit that predicts the number of accesses and inter-level movements.Using a full-system simulation including OS interactions and hardware overheads, we show that SLIP saves 35% energy at the L2 and 22% energy at the L3 level and performs 0.75% better than a regular cache hierarchy in a single core system. When configured to include a bypassing policy, SLIP reduces traffic to DRAM by 2.2%. This is achieved at the cost of storing 12b metadata per cache line (2.3% overhead), a 6b policy in the PTE, and 32b distribution metadata for each page in the DRAM (a overhead of 0.1%). Using SLIP in a multiprogrammed system saves 47% LLC energy, and reduces traffic to DRAM by 5.5%.

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“…The SRAM banks were modeled as being similar to that of the Intel R Xeon R E5 processor LLC design [19]. The L2 is modeled as a 2 (wide) ×4 (high) array of 32KB SRAM banks.…”

Section: Methodsmentioning

confidence: 99%

Section: Cache Organizationsmentioning

confidence: 99%

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Slip

Das

Aamodt

Dally

2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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“…We provide a brief overview of a cache's geometry in a modern processor. Figure 3 illustrates a multi-core processor modeled loosely after Intel's Xeon processors [14], [15]. Shared Last Level Cache (LLC) is distributed into many slices (14 for Xeon E5 we modeled), which are accessible to the cores through a shared ring interconnect (not shown in figure).…”

Section: Cache Geometrymentioning

confidence: 99%

“…We observe that LLC access latency is dominated by wire delays inside a cache slice, accessing upper-level cache control structures, and network-on-chip. Thus, while a typical LLC access can take ∼30 cycles, an SRAM array access is only 1 cycle (at 4 GHz clock [14]). Fortunately, in-situ architectures such as Neural Cache require only SRAM array accesses and do not incur the overheads of a traditional cache access.…”

Section: Cache Geometrymentioning

confidence: 99%

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

Eckert

Wang

et al. 2019

IEEE Micro

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This paper presents the Neural Cache architecture, which re-purposes cache structures to transform them into massively parallel compute units capable of running inferences for Deep Neural Networks. Techniques to do in-situ arithmetic in SRAM arrays, create efficient data mapping and reducing data movement are proposed. The Neural Cache architecture is capable of fully executing convolutional, fully connected, and pooling layers in-cache. The proposed architecture also supports quantization in-cache.Our experimental results show that the proposed architecture can improve inference latency by 18.3× over state-of-art multi-core CPU (Xeon E5), 7.7× over server class GPU (Titan Xp), for Inception v3 model. Neural Cache improves inference throughput by 12.4× over CPU (2.2× over GPU), while reducing power consumption by 50% over CPU (53% over GPU).

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Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

Korikawa

Kawabata

et al. 2020

IEEE Access

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Packet processing performance of Network Function Virtualization (NFV)-aware environment depends on the memory access performance of commercial-off-the-shelf (COTS) hardware systems. Table lookup is a typical example of packet processing, which has a significant dependence on memory access performance. Thus, the on-chip cache memories of the CPU are becoming more and more critical for many high-performance software routers or switches. Moreover, in the carrier network, multiple applications run on top of the same hardware system in parallel, which requires the capacity of cache memories. In this paper, we propose a packet processing architecture that enhances memory access parallelism by combining on-chip last-level-cache (LLC) slices and off-chip interleaved 3 Dimensional (3D)-stacked Dynamic Random Access Memory (DRAM) devices. Table entries are stored in the off-chip 3D-stacked DRAM, so that memory requests are processed in parallel by using bank interleaving and channel parallelism. Also, cached entries are distributed to on-chip LLC slices according to a memory address-based hash function so that each CPU core can access on-chip LLC in parallel. The evaluation results show that the proposed architecture reduces the memory access latency by 62 % and 12 % and increases the throughput by 108 % and 2 % with reducing blocking probability of memory requests 96 % and 50 %, compared to the architecture with on-chip shared LLC and that without on-chip LLC, respectively.

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An Energy Efficient 32-nm 20-MB Shared On-Die L3 Cache for Intel® Xeon® Processor E5 Family

Cited by 23 publications

References 2 publications

Slip

Slip

Neural Cache: Bit-Serial In-Cache Acceleration of Deep Neural Networks

Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM

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