An energy efficient and high speed architecture for convolution computing based on binary resistive random access memory

Abstract

In this work we present a novel convolution computing architecture based on metal oxide resistive random access memory (RRAM) to process the image data stored in the RRAM arrays. The proposed image storage architecture shows performances of better speed-device consumption efficiency compared with the previous kernel storage architecture. Further we improve the architecture for a high accuracy and low power computing by utilizing the binary storage and the series resistor. For a 28 ' 28 image and 10 kernels with a size of 3 ' 3, compared with the previous kernel storage approach, the newly proposed architecture shows excellent performances including: 1) almost 100% accuracy within 20% LRS variation and 90% HRS variation; 2) more than 67 times speed boost; 3) 71.4% energy saving.

1.2 nJ/classification 2.4 mm2 asynchronous wired-logic DNN processor using synthesized nonlinear function blocks in 0.18 μm CMOS

“…6) To solve such energy problems encountered in AI hardware, there has been active research aimed at developing processors that are more suitable for AI processing than von-Neumann-type hardware. [6][7][8][9][10][11][12][13][14][15][16] These studies focus on the fact that conventional von-Neumann processors consume significant power mainly due to frequent memory accesses. 17) This low efficiency of memory access stems from several reasons.…”