An Energy-Efficient and Robust Voltage Level Converter for Nanoelectronics

Abstract

Low-power design has recently become very important especially in nanoelectronic VLSI circuits and systems. Functioning of circuits at ultra-low voltages leads to lower power consumption per operation. An efficient method is to separate the logic blocks based on their performance requirement and applying a specific supply voltage for each block. In order to prevent an enormous static current in these multi-VDD circuits, voltage level converters are essential. This study presents an energy-efficient and robust single-supply level converter (SSLC) based on multi-threshold carbon nanotube FETs (CNTFETs). Unique characteristics of the CNTFET device and transistor stacking are utilized suitably to reduce the power and energy consumption of the proposed LC. The results of the extensive simulations, conducted using 32nm CNTFET technology of Stanford University indicate the superiority of the proposed design in terms energy-efficiency and robustness to process, voltage and temperature variations, as compared to the other conventional and state-of-the-art LC circuits, previously presented in the literature. The results demonstrate almost on average 35%, 55%, 90% and 68% improvements in terms of delay, total power, static power and energy consumption, respectively.

Design of a Radiation Hardened Register File for Highly Reliable Microprocessors

“…In this approach, radiation tolerance is obtained by a new design in circuit level. Radiation hardening by design can offer a high degree of reliability at the expense of a low design overhead [21][22]. However, they need specific fabrication process and high nonrecurring engineering (NRE) cost.…”

“…Similar to relations 1 to 4, we can derive the error probability for the DMR (shown in Fig.2) and 5MR techniques. The relevant equations are: (5) And: (6) To calculate the error probability of our proposed circuit, it is considerable that our structure can mask 1 and 2-bit errors while the TMR can mask only one error. Therefore, the equation for error probability of a w-bit word is obtained by (7).…”

“…High energy particles striking the sensitive nodes of an static random access memory (SRAM) cell, could cause a bit upset and result in operation failure [1][2][3][4][5][6]. The phenomenon of a bit flip in a memory cell such as a flip-flop or latch induced by a particle strike is called single-event upset (SEU).…”

“…Technology shrinking that comes with decrease in supply voltage, affects the sensitivity of the SRAM cells to soft errors [5][6][7][8]. Fig.1 depicts the relation between the technology size, supply voltage and Q crit (the minimum charge needed for a particle strike to result in an SEU).…”

“…The phenomenon of a bit flip in a memory cell such as a flip-flop or latch induced by a particle strike is called single-event upset (SEU). When an energetic particle hits more than one memory cell and causes more than one bit flip, a multi-bit upset (MBU) is happened [6][7][8].…”