An energy-efficient coarse-grained dynamically reconfigurable fabric for multiple-standard video decoding applications

Optimizing Spatial Mapping of Nested Loop for Coarse-Grained Reconfigurable Architectures

“…Since these key nested [21]. When normalized to the same process, ReMUS_LPP [8] still outperforms ADRES 1.58× in energy efficiency. The effective mapping of key nested loops onto ReMUS hardware by PolyMap makes an important contribution to the outstanding energy efficiency.…”

“…The implementation of this interlayer bus is diverse. For example, the interlayer bus in ReMUS [8] is actually a crossbar composed of multiplexors and wires and no additional clock cycles are needed to transfer data between two nearby rows once the routing style is configured. With the crossbar interconnections, a PE could connect to total 16 PEs from its precursor row and successor row in an 8 × 8 PEA.…”

“…Hence, the last PE at the end of the configuration chain would be set after at most row + column cycles, where row and column are the coordinate of the PE. In reconfigurable multimedia processor (ReMUS) [8], ∼4 cycles are needed as the configuration bandwidth is 1024 bits/cycle, whereas the number of configuration bits of a PEA operation is ∼3600 bits. Actually, the configuration cost is the tradeoff between interconnection flexibility and power consumption.…”

“…The interconnection topology of PEA also has a great variety, which could be further categorized into two types [9] according to the interconnection scheme: 1) array-based PEA [6], [10]- [12]; and 2) row-based PEA [8], [13], [14]. The routing topologies in array-based CGRAs are usually mesh or mesh-plus, where each PE could connect to its four or eight neighbors.…”

“…To demonstrate the effectiveness of the proposed loop nests mapping method, we conduct some experiments on ReMUS_LPP processor [8]. It is a reconfigurable media computing processor, which is composed of a host controller and a reconfigurable processor unit (RPU).…”