An energy-efficient FDCT/IDCT configurable IP core for mobile multimedia platforms

Abstract

The development of mobile multimedia devices follows the platform-based design methodology in which IP cores are the building blocks. In the context of mobile devices there is a concern of battery lifetime which leads to the need of energyefficient IP cores. This paper presents an energy-efficient FDCT/IDCT configurable IP core. Synthesis for 90 nm resulted in 50 MHz as maximum frequency and 1.66 mW as total power, achieving a throughput of 188.2 Mpixels/s, which is enough to process two HDTV@1080p videos in real time. The IP core architecture is based on Massimino's algorithm, which was chosen for its accuracy and parallelism. The exploration of its parallelism resulted in a fully-combinational 1-D FDCT/IDCT configurable datapath. In addition, the IP core is IEEE-1180 compliant. Comparisons with related work, in terms of energy efficiency (mJ/Mpixel), revealed that our architecture is at least 64% more efficient than other DCT architectures.

Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores

“…Evaluating the Impact of Architectural Decisions on the Energy Efficiency of FDCT/IDCT Configurable IP Cores Livramento, Moraes, Machado, Boabaid, & Güntzel pipelined version needs four more cycles of latency to compute an entire matrix. For further details on the design of the configurable 1xD DCT Comb, refer to [31]. Figure 13 shows the 1xDCT Comb block diagram.…”

“…It also provides the required frequencies considering the two target throughputs estimated in Section 1: 124.3 MPixels/s for 1080p@30fps (4:2:2 subsampling) and 18.4 MPixels/s for VGA@30fps (4:2:2 subsampling). It is worth mentioning that in our previous work [31] the 1xDCT Comb architecture was synthesized and evaluated targeting a throughput of 93.3 MPixels/s for 1080p@30fps (4:2:0 subsampling).…”