An energy‐efficient level shifter based on a differential cascade voltage switch structure

Abstract

Based on differential cascade voltage switch architecture, this paper proposes a level shifter with optimized energy consumption, constructed by stacking diode‐connected NMOS and PMOS transistors and splitting input signals of the two output stages. Eventually, the overlap time of input signals of the two output stages has been reduced, during which there is a considerable short‐current from high voltage source to ground. When implemented in a 110 nm CMOS process, post‐layout netlist simulations show that the proposed level shifter exhibits a 2.31 ns switching delay and 819 fJ energy consumption when converting a 1.5 V input signal into 4.5 V with 10 MHz operational frequency and 15 fF output load.