An Energy-Efficient Network-on-Chip-Based Reconfigurable Viterbi Decoder Architecture

Implementation of high throughput system for data correction

“…Established ECC require specialized hardware whose nature hampers its throughput. Authors of [2] offer a comparison of stateof-the-art Viterbi decoders. None of these designs can surpass 13 Gbps of throughput.…”

Implementation of high throughput system for data correction

“…The throughput of the parallelization is 750 MHz× (40×5) bits =150 GHz for the first set and 750 MHz× (30×10) bits=225Gbps. In [2] authors compare different architectures of Viterbi encoders (the primary hardware implementation used for error correction) while proposing a new scheme that surpasses all. In table 6 there is a comparison between our design and the author's work.…”

“…Nearly all iterations of ECC use the Viterbi algorithm [1] in some form for their hardware implementation. The translation of the Viterbi algorithm to hardware form is an arduous process and the resulting circuits often do not have high throughput [2]. Finally, for ECC to be effective and efficient, they need to be specialized.…”

Implementation of high throughput system for data correction

“…Power consumption is around 14 times larger on FPGA. The difference in technology (90nm vs 16nm) was also be factored in proportionally giving us the final normalized values for 90nm technology (used in [2]). In terms of error correction, our circuit is much smaller and faster.…”