An enhanced 16nm CMOS technology featuring 2&lt;sup&gt;nd&lt;/sup&gt; generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

Wu, Shien‐Yang; Lin, Chih‐Yu; Chiang, Meng-Hsueh; Liaw, J.J.; Cheng, J.Y.; Yang, Shixuan; Chang, Shu-Wei; Liang, Mei; Miyashita, T.; Tsai, C.S.; Chang, Chih-Hsien; Chang, V.S.; Wu, Yi-Ting; Chen, J.H.; Chen, H.F.; Pan, K.H.; Tsui, R.F.; Yao, C.H.; Ting, Kong; Yamamoto, Tsuyoshi; Huang, Hao; Lee, T.L.; Lee, C.H.; Chang, W.; Lee, H.M.; Chen, C.C.; Chang, Tzu-Heng; Chen, R.; Chiu, Yi-Hung; Tsai, Ming-Hsien; Jang, S. M.; Chen, K.S.; Ku, Yao-Ching

doi:10.1109/iedm.2014.7046970

Cited by 38 publications

(14 citation statements)

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“…The traditional design approach of guaranteeing circuit integrity by simulating over all process corners can result in so much guard-banding that the design becomes severely compromised within the available constraints [11] [12]. Improved models should support Design Technology Co-Optimization (DTCO), which has become 'must' in advanced CMOS [13]- [16]. They should also allow the yield to be factored in the analysis and verification and should enable performance/power/area/yield (PPAY) trade off and sign off [17] [18].…”

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confidence: 99%

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

Wang

Cheng

Reid

et al. 2015

IEEE Trans. Electron Devices

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Abstract-In this paper we present a FinFET focused variability-aware compact model extraction and generation technology supporting design-technology co-optimization (DTCO). 14-nm CMOS technology generation SOI FinFETs are used as test-bed transistors to illustrate our approach. The TCAD simulations include long-range process-induced variability using a design of experiment (DoE) approach and short-range purely statistical variability (

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confidence: 99%

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

Wang

Cheng

Reid

et al. 2015

IEEE Trans. Electron Devices

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“…1(a)) and contact resistance . Solid curves: (3). Dashed curves: corresponding to the source side resistance network illustrated in Fig.…”

Section: Discussion and Summarymentioning

confidence: 99%

Modeling of Resistance in FinFET Local Interconnect

Wachnik

2015

IEEE Trans. Circuits Syst. I

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We present an innovative and comprehensive approach to model the resistance of local interconnect used in FinFET technologies. Our parasitic resistance formulas for FinFET source/drain regions cover both merged and unmerged fin processes. Both simple and composite local interconnect cases are studied. They have been verified with field solver simulation results, and are found to be accurate over a wide range of parameter values. Our local interconnect resistance model has been used in IBM 14 nm SOI FinFET CMOS technology, and is a critical part of compact models used in both extraction flow and schematic/pre-layout flow.

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“…The hardware used in this study is manufactured with advanced dual damascene Cu/low-K ULSI technology The details of these processes were presented in [12][13]. Test structure has a metal width of 50nm or narrower and metal length of 250 micrometer.…”

Section: Methodsmentioning

confidence: 99%

Study of a new electromigration failure mechanism by novel test structure

Chen

Lin

Hsieh

et al. 2015

2015 IEEE International Reliability Physics Symposium

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A novel electromigration (EM) structure is designed and characterized with advanced Cu/low-k technology. Comparing the EM results derived from novel and traditional test structures, a new EM failure mechanism is proposed. The new mechanism is caused by the Cu/barrier interface damage at the metal line-edge during upper Via opening process. This damage provides a fast diffusion path. From the downstream EM test, it is observed that the thicker Ta-based ALD barrier has a higher activation energy and median time to failure compared to thinner Ta based barrier. Thicker barrier process enhances Cu/barrier adhesion and hence prevent the via opening induced interface damage.

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An enhanced 16nm CMOS technology featuring 2<sup>nd</sup> generation FinFET transistors and advanced Cu/low-k interconnect for low power and high performance applications

Cited by 38 publications

References 1 publication

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

FinFET Centric Variability-Aware Compact Model Extraction and Generation Technology Supporting DTCO

Modeling of Resistance in FinFET Local Interconnect

Study of a new electromigration failure mechanism by novel test structure

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