An Enhanced Bit-line Keeper for Computational Memory Architecture

Azougagh, Driss; Rebbani, Ahmed; Bouattane, Omar

doi:10.1109/syscobiots48768.2019.9028042

Cited by 1 publication

(5 citation statements)

References 11 publications

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“…In particular, a detailed study and analysis of the functionality and behavior of minimal CL (M-CL) are introduced. These basics are the ones exploited to design the full version of the compute-line supporting built-in computational capabilities in [1] from which other derivations with different optimization objectives and purposes emerged in [2]- [4]. Extending the finding in this work to [2] is straight forward and to [3], [4] requires some study left for future work.…”

Section: Ccma Basicsmentioning

confidence: 99%

“…These basics are the ones exploited to design the full version of the compute-line supporting built-in computational capabilities in [1] from which other derivations with different optimization objectives and purposes emerged in [2]- [4]. Extending the finding in this work to [2] is straight forward and to [3], [4] requires some study left for future work. The M-INPUT has one nMOS transistor (XN) and one AND logic gate (XG).…”

Section: Ccma Basicsmentioning

confidence: 99%

“…When XSL is activated, M-CL senses for any participating M-CMC (M-INPUT) pulling down the bit-line XBL to 0 while the M-KEEPER keeps raising non pulled down XBL to 1 and projecting the opposite state of XBL to YBL, as formulated in the two expressions in (1). Once both bit-lines are stabilized, targeted M-CMCs (M-OUTPUTs) save the resulting state to their storage nodes using the expression in (2).…”

Section: Ccma Basicsmentioning

confidence: 99%

“…In contrary, CL does not require dedicated computational, pre-charging and/or sensing circuitry logics to conduct a logical operation on locally stored data without any memory copy. Instead, it uses at request [1] or automatically [2]- [4] a bit-line keeper (KEEPER) to keep both bit-lines stable and superposed to each other for each execution of an elementary operation (NAND/NOR/NOT) on the selected data stored locally.…”

Section: Introductionmentioning

confidence: 99%

“…It supports in bit-line processing bringing parallel computation as close as possible to the location of the stored data. It first selects and sets up an operation, reads bit information from external inputs and/or local memory cells in parallel and simultaneously, stabilizes the bit-lines throughout the controlled [1] or automated [2]- [4] KEEPER, and finally writes the data to external outputs and/or local memory cells in one compute cycle. Moreover, multiple CLs can be interconnected using dedicated topologies with multiple dimensions to accelerate computation and increase locality for specific research areas.…”

Section: Introductionmentioning

confidence: 99%

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A Compute-line based Computational Memory Architecture using bit-line Keepers: Internals and Analysis

Azougagh¹

2020

IJATCSE

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The growth of Big Data, memory wall and power wall are posing unprecedented demand for Processing In Memory (PIM). A computational memory architecture supporting in bit-Line processing can be a major key for PIM to eliminate the overhead of moving data from processing unit to memory and vice versa. It promises high bandwidth, massive parallelism, and high energy efficiency. The existing PIM approaches concentrates mostly on near-memory processing (NMP) and/or in-memory processing (IMP). The Compute-line based Computational Memory Architecture (CCMA), or simply (multiple) compute-lines (CLs), represents a different way of approaching in-memory processing (IMP). A compute-line represents a line that carries fine-grained operations using connected memory cells. CL is based on (a selection of) a bit-line for processing elementary logical operations and a bit-line Keeper (KEEPER) for enforcing and stabilizing the outcome results. CCMA is backward compatible with the conventional Static Random Access Memory (SRAM) and can be used for state storing. In contrary to the conventional SRAM, it eliminates the need to pre-charge and sensing bit-line(s) for read and write operations which reduces bit-line activities and support in-place combinational logic which reduces data transfer latency. It introduces a considerable potential to reduce bandwidth and energy consumption by eliminating overhead of data movement when used as an in-memory computing. Moreover, it can easily support any specific interconnect topology between multiple compute-lines for parallel applications by hard wiring their input/output interfaces during chip fabrication. The CCMA designs the KEEPER circuitry so that, in one (or two) clock cycle(s) and through bit-line selection, its can multi-row read bit information from participating memory cells, bitwise logic compute selected operation and multi-row write to targeted memory cells. In this work, toward deep investigation of the CCMA architectures and perspective remarks, CL's capabilities and statistical analysis of running in-place logic operations are presented and showed potential computational and global energy savings.

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