An enhanced dual-path ΔΣ analog-to-digital converter

Abstract

This paper presents an enhanced dual-path deltasigma ADC. The first-order enhancement of the quantization noise shaping is achieved by employing a switched capacitor circuit technique. A test chip, fabricated in a 0.18-µm CMOS process, provides a signal-to-noise+distortion ratio (SNDR) of 75-dB for a 1.0-MHz signal bandwidth clocked at 40-MHz. The 2 nd harmonic is -101-dB and the 3 rd one is -94-dB when a -4.5-dB 100-kHz input signal is applied. I.978-1-4244-3828-0/09/$25.00 ©2009 IEEE