An Enhanced Network-on-chip Simulation for Cluster-based Routing

Hassan, Ahmed S.; Morgan, Ahmed A.; El-Kharashi, M. Watheq

doi:10.1016/j.procs.2016.08.063

Cited by 5 publications

(5 citation statements)

References 7 publications

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“…This paper is a significant extension and update of a paper that appeared in the proceedings of the Workshop on Design and Performance of Networks on Chip (DPNoC 2016) in conjunction with the The 11th International Conference on Future Networks and Communications (FNC 2016) [31]. All trademarks ™ and registered trademarks ® mentioned, cited, or referenced in this document remain the property of their respective owners.…”

Section: Acknowledgmentmentioning

confidence: 93%

Clustered Networks-on-Chip: Simulation and Performance Evaluation

Hassan¹

2017

IJCDS

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In many-core Networks-on-Chip (NoC) systems, two topics have recently been researched; NoC clustering and NoC simulation. NoC clustering investigates grouping processing elements (PEs) based on common characteristics between them, like spatial locality or communication patterns. Research showed that NoC clustering achieved better performance and load balancing. Furthermore, it allows scalability of the NoC grid. The other topic, NoC simulation, provides tools for early evaluation of NoC systems. This allowed easy investigation of NoC systems with large number of PEs. Plenty of research has been done in both topics separately. In this paper, we try to fill the gap. We extend an existing NoC simulation tool by adding support for simulating NoC clusters and inter-NoC traffic. The presented NoC clustering simulator supports the modular design technique, which in turn offers the flexibility in configuring cluster parameters. Examples of configurable parameters that are supported by our modified simulator are: adding interconnection topologies to configure how the NoC entities are connected with each other, adding a cluster manager that maps tasks to NoC entities based on the inter-NoC communication pattern, adding latency factors of cluster links in the case of inter-NoC traffic, and adapting the routing algorithm for both inter-cluster and intra-cluster traffic. A clustered NoC simulation case study shows the effectiveness of the modifications made to the simulator. For example, a certain NoC setup is simulated twice, initially non-clustered then clustered, using the added features. Collected data shows that the average clustered NoC routers' energy consumption is 50% lower than the consumption in the non-clustered case.

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Section: Acknowledgmentmentioning

confidence: 93%

Clustered Networks-on-Chip: Simulation and Performance Evaluation

Hassan¹

2017

IJCDS

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“…The extended NoCTweak simulator [46,47] is used for all our simulation experiments in this paper. To the best of our knowledge, this simulator is the only one that allows NoCbased systems to be interfaced to each others with different degrees of inter-connectivity.…”

Section: B Simulation Environmentmentioning

confidence: 99%

NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

et al. 2020

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Current research in interfacing clusters within Hierarchical Networks-on-Chip (HNoC) as well as interfacing NoC-based systems adopts a centralized approach. In this approach, a specific Processing Element (PE) acts as a gateway between interfacing peripherals and the rest of NoC elements. This paper evaluates this approach and show that it is not optimal for handling the inter-NoC communication. Routing inter-NoC traffic through a system to its gateway PE deteriorates the network performance. Results show that both the throughput and latency of the centralized approach degrade with the increase in the inter-NoC traffic bandwidth. To alleviate this, we propose a novel distributed approach, which separates the inter-NoC traffic from the intra-NoC one. Our approach relies on distributed buffers to allow PEs to efficiently communicate with the interfacing peripheral. We evaluate our approach against other interfacing ones using synthetic traffic as well as real benchmark applications. Our evaluation covers the whole system performance as well as its inter-and intra-NoC parts. Results prove that the proposed approach outperforms previous interfacing ones in terms of throughput and latency. The proposed approach significantly enhances the inter-NoC performance without any deterioration in the intra-NoC one. Considering the inter-NoC performance, we achieve a throughput that is close to the maximum possibly attainable one. Other approaches show major performance degradation, reaching as low as 10% of this maximum attainable throughput. INDEX TERMS Hierarchical Networks-on-Chip (HNoC), Inter-NoC communication, Intra-NoC communication, NoC benchmarks, NoC Ethernet, NoC high-speed interfacing, NoC Time Division Multiple Access (TDMA), NoC traffic.

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“…In order to simulate our system, we added support for clustering simulation to one of the NoC simulators. In our previous work, we extended a NoC simulator, NoCTweak [26], so that it would support cluster simulation [27], [28].…”

Section: Related Workmentioning

confidence: 99%

“…By using the tool proposed in our previous study [27], [28], we managed to simulate the case of inter-NoC traffic. The aim of this simulation was to evaluate the performance of the intuitive inter-NoC communication technique; routing the outbound traffic to the edge PEs.…”

Section: B Case Studymentioning

confidence: 99%

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

Hassan¹

2017

IJCDS

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Many-and multi-core Networks-on-Chip (NoC) systems have a large spectrum of applications, and one of these applications is High Performance Computing (HPC). In HPC application, system scalability is one of the important features of a given HPC platform. Two of the factors governing scalability are the interfacing link speed and the ease of deploying additional processing nodes. For NoC-based systems, scalability has two meanings; intra-NoC scalability, which includes partitioning and clustering Processing Elements (PEs) to achieve better performance, and inter-NoC scalability, which includes interfacing with other NoC-based systems via inter-NoC links and creating a newtrok of multiple NoC-based systems. In this paper, we investigate the case of inter-NoC communication between a network of NoC-based systems. By using our simulator, we found out that treating a network of NoC-based systems as a generic case of interfacing yields non-optimal performance. To target the inter-NoC communication performance, we introduce NoC 2 , an NoC-based system with an Ethernet communication manager that provides better management for inter-NoC traffic. Current implementations of inter-NoC traffic management handle inter-NoC traffic using software running on top of a dedicated PE, whereas NoC 2 is designed so that the software running on cores within the NoC is completely abstracted from inter-NoC traffic management. Experiments show that this kind of abstraction has better inter-NoC communication performance over generic NoC interfaced via Ethernet. Results suggest that NoC 2 would perform better when it comes to scaling NoC-based systems by interfacing more NoC-based hardware.

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An Enhanced Network-on-chip Simulation for Cluster-based Routing

Cited by 5 publications

References 7 publications

Clustered Networks-on-Chip: Simulation and Performance Evaluation

Clustered Networks-on-Chip: Simulation and Performance Evaluation

NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

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An Enhanced Network-on-chip Simulation for Cluster-based Routing

Cited by 5 publications

References 7 publications

Clustered Networks-on-Chip: Simulation and Performance Evaluation

Clustered Networks-on-Chip: Simulation and Performance Evaluation

NoC2: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems

Networks-on-Chip Interfacing: NoC-based Systems Networking and Inter-NoC Communication

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NoC²: An Efficient Interfacing Approach for Heavily-Communicating NoC-Based Systems