An enhanced template matching algorithm and its chip implementation

Abstract

This paper presents an enhanced template matching algorithm and its chip implementation. T h e proposed algorithm called the enhanced moment preserving pattern matching (EMPPM) improves the noise margin by 22% compared with the previously proposed algorithm called the moment preserving pattern matching (MPPM) algorithm. In addition, the proposed architecture can reduce the gate count by more than 28% compared with the MPPM architecture. W e have implemented behavior and structure models using VHDL and performed logic synthesis using the SynopsysTR' CAD tool. The actual chip has been implemented using the SarnsungTh' 0.6pm SOG (sea-of-gate) cell library. The implemented chip consists of 35,827 gates, operates a t 100 MHz and performs 16x16 template matching with the speed of 200 Mpixelshec.