An Enhancement-Mode GaN p-FET With Improved Breakdown Voltage

Jin, Hao; Jiang, Qimeng; Huang, Sen; Wang, Xinhua; Wang, Yingjie; Ji, Zhongchen; Dai, Xinyue; Feng, Chao; Fan, Jie; Ke, Wei; Liu, Jianxun; Zhong, Yaozong; Sun, Qian; Liu, Xinyu

doi:10.1109/led.2022.3184998

Cited by 28 publications

(6 citation statements)

References 30 publications

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“…This involves utilizing electron beam lithography to form the "distribute-recessed via" at the bottom of the conventional gate trench, followed by the realization of n-ohmic contact for back gate (along with ohmic contacts for the integrated n-channel devices) at high temperatures. After that, the remaining low-temperature processing steps are conducted, which is consistent with the typical process sequence for conventional GaN p-MISFETs, as reported in experimental works [38]. All the aforementioned steps are compatible with the current process of fabricating commercial n-channel p-GaN gate HEMTs.…”

Section: Switching Characteristics Of the Complementary Logic Invertersmentioning

confidence: 61%

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

Wang,

Chen,

Yang

et al. 2024

Electronics

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In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC.

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Section: Switching Characteristics Of the Complementary Logic Invertersmentioning

confidence: 61%

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

Wang,

Chen,

Yang

et al. 2024

Electronics

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“…The excellent V TH stability benefits from the Si-rich LPCVD-SiN x used for gate dielectric. The Si-rich LPCVD-SiN x leaves high-density Near-Conduction-Band (NCB) Si-rich LPCVD-SiN x /Ⅲ-V interface states, which are ionized and act as fixed positive charges [21] . As illustrated in Fig.…”

Section: Resultsmentioning

confidence: 99%

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN_x gate insulator for high hole mobility

Zhu,

Chen,

et al. 2023

J. Semicond.

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In this work, the GaN p-MISFET with LPCVD-SiN x is studied as a gate dielectric to improve device performance. By changing the Si/N stoichiometry of SiN x , it is found that the channel hole mobility can be effectively enhanced with Si-rich SiN x gate dielectric, which leads to a respectably improved drive current of GaN p-FET. The record high channel mobility of 19.4 cm2/(V∙s) was achieved in the device featuring an Enhancement-mode channel. Benefiting from the significantly improved channel mobility, the fabricated E-mode GaN p-MISFET is capable of delivering a decent-high current of 1.6 mA/mm, while simultaneously featuring a negative threshold-voltage (V TH) of –2.3 V (defining at a stringent criteria of 10 μA/mm). The device also exhibits a well pinch-off at 0 V with low leakage current of 1 nA/mm. This suggests that a decent E-mode operation of the fabricated p-FET is obtained. In addition, the V TH shows excellent stability, while the threshold-voltage hysteresis ΔV TH is as small as 0.1 V for a gate voltage swing up to –10 V, which is among the best results reported in the literature. The results indicate that optimizing the Si/N stoichiometry of LPCVD-SiN x is a promising approach to improve the device performance of GaN p-MISFET.

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“…The hole sheet density and mobility were measured to be 2.3 × 10 13 cm −2 and 11. [26,27] . The introduction of the 5-nm O 3 -Al 2 O 3 insertion layer can effectively reduce the leakage of the O 3 -Al 2 O 3 /HfO 2 stack and improve its voltage-blocking capability.…”

Section: Epitaxial Structure and Dielectric Leakage Characterizationmentioning

confidence: 99%

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

Jin,

Huang,

Jiang

et al. 2023

J. Semicond.

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In this letter, an enhancement-mode (E-mode) GaN p-channel field-effect transistor (p-FET) with a high current density of −4.9 mA/mm based on a O3-Al2O3/HfO2 (5/15 nm) stacked gate dielectric was demonstrated on a p++-GaN/p-GaN/AlN/AlGaN/AlN/GaN/Si heterostructure. Attributed to the p++-GaN capping layer, a good linear ohmic I−V characteristic featuring a low-contact resistivity (ρ c) of 1.34 × 10−4 Ω·cm2 was obtained. High gate leakage associated with the HfO2 high-k gate dielectric was effectively blocked by the 5-nm O3-Al2O3 insertion layer grown by atomic layer deposition, contributing to a high I ON/I OFF ratio of 6 × 106 and a remarkably reduced subthreshold swing (SS) in the fabricated p-FETs. The proposed structure is compelling for energy-efficient GaN complementary logic (CL) circuits.

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An Enhancement-Mode GaN p-FET With Improved Breakdown Voltage

Cited by 28 publications

References 30 publications

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN_x gate insulator for high hole mobility

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric

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An Enhancement-Mode GaN p-FET With Improved Breakdown Voltage

Cited by 28 publications

References 30 publications

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

A Novel Enhancement-Mode Gallium Nitride p-Channel Metal Insulator Semiconductor Field-Effect Transistor with a Buried Back Gate for Gallium Nitride Single-Chip Complementary Logic Circuits

High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN x gate insulator for high hole mobility

High-performance enhancement-mode GaN-based p-FETs fabricated with O3-Al2O3/HfO2-stacked gate dielectric

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High threshold voltage enhancement-mode GaN p-FET with Si-rich LPCVD SiN_x gate insulator for high hole mobility

High-performance enhancement-mode GaN-based p-FETs fabricated with O₃-Al₂O₃/HfO₂-stacked gate dielectric