An evaluation of a commercial CC-NUMA architecture-the CONVEX Exemplar SPP1200

Thekkath, Radhika; Singh, Arashdeep; Singh, Jaswinder Pal; John, Sonya; Hennessy, John L.

doi:10.1109/ipps.1997.580831

Cited by 15 publications

(6 citation statements)

References 13 publications

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“…The trend is very clear and our results confirm what has been shown before [4,16,30]: having a large remote access cache is important. CRASH with a 256MB DRAC is compa-…”

Section: Dram Write-back / Rac Sizesupporting

confidence: 90%

“…For example, Sequent's NUMA-Q [18] and Stanford's DASH [16] both have hardware controlled fixedsize remote access caches. In-memory remote access caches have been tested in Stanford's FLASH [14] and Convex's Exemplar [2,30]. Since the FLASH design is based on a software coherence protocol run on the coherence processor the remote access cache size and its layout are trivial to change.…”

Section: Related Workmentioning

confidence: 99%

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A case for low-complexity MP architectures

Zeffer

Hägersten

2007

Proceedings of the 2007 ACM/IEEE Conference on Supercomputing

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Advances in semiconductor technology have driven sharedmemory servers toward processors with multiple cores per die and multiple threads per core. This paper presents simple hardware primitives enabling flexible and low-complexity multi-chip designs supporting an efficient inter-node coherence protocol implemented in software.We argue that our primitives and the example design presented in this paper have lower hardware overhead, have easier (and later) verification requirements, and provide the opportunity for flexible coherence protocols and simpler protocol bug corrections than traditional designs.Our evaluation is based on detailed full-system simulations of modern chip-multiprocessors and both commercial and HPC workloads. We compare a low-complexity system based on the proposed primitives with aggressive hardware multi-chip shared-memory systems and show that the performance is competitive across a large design space.

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“…The trend is very clear and our results confirm what has been shown before [4,16,30]: having a large remote access cache is important. CRASH with a 256MB DRAC is compa-…”

Section: Dram Write-back / Rac Sizesupporting

confidence: 90%

Section: Related Workmentioning

confidence: 99%

A case for low-complexity MP architectures

Zeffer

Hägersten

2007

Proceedings of the 2007 ACM/IEEE Conference on Supercomputing

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“…The idea of employing caches to mitigate NUMA effects has been proposed previously in cache-only-memory architecture (COMA) [8], [38], [39], [40] and tertiary caching [41], [42], [43]. In tertiary caching, a fixed size of the local node's memory is used as a hardware managed cache that caches only remotely allocated blocks.…”

Section: Tertiary Caching and Comamentioning

confidence: 99%

C³D: Mitigating the NUMA bottleneck via coherent DRAM caches

Huang¹,

Kumar²,

Elver³

et al. 2016

2016 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Massive datasets prevalent in scale-out, enterprise, and high-performance computing are driving a trend toward ever-larger memory capacities per node. To satisfy the memory demands and maximize performance per unit cost, today's commodity HPC and server nodes tend to feature multi-socket shared memory NUMA organizations. An important problem in these designs is the high latency of accessing memory on a remote socket that results in degraded performance in workloads with large shared data working sets.This work shows that emerging DRAM caches can help mitigate the NUMA bottleneck by filtering up to 98% of remote memory accesses. To be effective, these DRAM caches must be private to each socket to allow caching of remote memory, which comes with the challenge of ensuring coherence across multiple sockets and GBs of DRAM cache capacity. Moreover, the high access latency of DRAM caches, combined with high inter-socket communication latencies, can make hits to remote DRAM caches slower than main memory accesses. These features challenge existing coherence protocols optimized for on-chip caches with fast hits and modest storage capacity. Our solution to these challenges relies on two insights. First, keeping DRAM caches clean avoids the need to ever access a remote DRAM cache on a read. Second, a non-inclusive on-chip directory that avoids tracking blocks in the DRAM cache enables a light-weight protocol for guaranteeing coherence without the staggering directory costs. Our design, called Clean Coherent DRAM Caches (C 3 D), leverages these insights to improve performance by 6.4-50.7% in a quad-socket system versus a baseline without DRAM caches.

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“…Tertiary Caching was proposed in the context of multisocket systems. In Tertiary Caching [76,85], a portion of each node's local memory is managed as a cache for caching only data objects that are allocated in remote nodes. While there are similarities between MemCache and Tertiary Caching, they are conceptually different.…”

Section: Related Workmentioning

confidence: 99%

Die-Stacked DRAM: Memory, Cache, or MemCache?

Bakhshalipour,

Zare,

Lotfi-Kamran

et al. 2018

Preprint

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Die-stacked DRAM is a promising solution for satisfying the ever-increasing memory bandwidth requirements of multi-core processors. Manufacturing technology has enabled stacking several gigabytes of DRAM modules on the active die, thereby providing orders of magnitude higher bandwidth as compared to the conventional DIMM-based DDR memories. Nevertheless, die-stacked DRAM, due to its limited capacity, cannot accommodate entire datasets of modern big-data applications. Therefore, prior proposals use it either as a sizable memory-side cache or as a part of the software-visible main memory. Cache designs can adapt themselves to the dynamic variations of applications but suffer from the tag storage/latency/bandwidth overhead. On the other hand, memory designs eliminate the need for tags, and hence, provide efficient access to data, but are unable to capture the dynamic behaviors of applications due to their static nature.In this work, we make a case for using the die-stacked DRAM partly as main memory and partly as a cache. We observe that in modern big-data applications there are many hot pages with a large number of accesses. Based on this observation, we propose to use a portion of the die-stacked DRAM as main memory to host hot pages, enabling serving a significant number of the accesses from the high-bandwidth DRAM without the overhead of tag-checking, and manage the rest of the DRAM as a cache, for capturing the dynamic behavior of applications. In this proposal, a software procedure pre-processes the application and determines hot pages, then asks the OS to map them to the memory portion of the die-stacked DRAM. The cache portion of the die-stacked DRAM is managed by hardware, caching data allocated in the off-chip memory. Through detailed evaluations of various big-data applications, we show that our proposal improves system performance by 28% and up to 139% over the previous best-performing proposal.

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An evaluation of a commercial CC-NUMA architecture-the CONVEX Exemplar SPP1200

Abstract: Abstract

Cited by 15 publications

References 13 publications

A case for low-complexity MP architectures

A case for low-complexity MP architectures

C³D: Mitigating the NUMA bottleneck via coherent DRAM caches

Die-Stacked DRAM: Memory, Cache, or MemCache?

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An evaluation of a commercial CC-NUMA architecture-the CONVEX Exemplar SPP1200

Abstract: Abstract

Cited by 15 publications

References 13 publications

A case for low-complexity MP architectures

A case for low-complexity MP architectures

C3D: Mitigating the NUMA bottleneck via coherent DRAM caches

Die-Stacked DRAM: Memory, Cache, or MemCache?

Contact Info

Product

Resources

About

C³D: Mitigating the NUMA bottleneck via coherent DRAM caches