An Event-Based, Digital Time Difference Encoder Model Implementation for Neuromorphic Systems

Abstract

Neuromorphic systems are a viable alternative to conventional systems for real-time tasks with constrained resources. Their low power consumption, compact hardware realization, and low-latency response characteristics are the key ingredients of such systems. Furthermore, the event-based signal processing approach can be exploited for reducing the computational load and avoiding data loss, thanks to its inherently sparse representation of sensed data and adaptive sampling time. In event-based systems, the information is commonly coded by the number of spikes within a specific temporal window. However, event-based signals may contain temporal information which is complex to extract when using rate coding. In this work, we present a novel digital implementation of the model, called Time Difference Encoder, for temporal encoding on event-based signals, which translates the time difference between two consecutive input events into a burst of output events. The number of output events along with the time between them encodes the temporal information. The proposed model has been implemented as a digital circuit with a configurable time constant, allowing it to be used in a wide range of sensing tasks which require the encoding of the time difference between events, such as optical flow based obstacle avoidance, sound source localization and gas source localization. This proposed bio-inspired model offers an alternative to the Jeffress model for the Interaural Time Difference estimation, validated with a sound source lateralization proof-of-concept. The model has been simulated and implemented on an FPGA, requiring 122 slice registers of hardware resources and less than 1 mW of power consumption.

Event-Based Sound Source Localization in Neuromorphic Systems

“…Our current system only uses two out of the 128 frequency channels. The eight subsequent TDEs on FPGA require approximately 1120 Registers and 1440 lookup tables with a power consumption of around 12 mW [13]. On SpiNNaker, the TDE input population of 8 neurons, the two Time to Rate Network output neurons, the 256 Ring Attractor Neurons and the 64 Center Detector Network neurons require two out of 18 cores on a single ARM chip.…”

“…While in this article we use a relatively large prototyping system consisting of three boards to evaluate the functionality of our SSL approach, our final aim is to implement the network onto a single mixed analogdigital asynchronous CMOS ASIC. Using the TDE on CMOS (1.4 nW-500 µW [13]), and the Low-power LIF neuron on CMOS (20 µW-100 µW for 100Hz [37]) we can aim at the design of a single ASIC with an overall power consumption in the double digit mW range or below. The implementation proposed in this article is, to the best of the authors' knowledge, the first neuromorphic hardware closed-loop SSL system using ITD capable of working in real time.…”

“…The applicability of this model for temporal encoding in vision and touch has already been demonstrated in [8], [9], [10], [11] and [12]. The TDE has been implemented in mixed digital/analog subthreshold CMOS hardware [8], only consuming between 1.4 nW (static) and 500 µW (dynamic) [13]. Its most recent Field Programmable Gate Array (FPGA) implementation uses 179 lookup tables and 140 registers, hardware resources comparable to other neuron models on FPGA [13].…”

“…The TDE has been implemented in mixed digital/analog subthreshold CMOS hardware [8], only consuming between 1.4 nW (static) and 500 µW (dynamic) [13]. Its most recent Field Programmable Gate Array (FPGA) implementation uses 179 lookup tables and 140 registers, hardware resources comparable to other neuron models on FPGA [13]. In this work, we evaluate the performance of an SSL neuromorphic system using the TDE on FPGA in a closed-loop demonstrator.…”

A Hardware-Friendly Neuromorphic Spiking Neural Network for Frequency Detection and Fine Texture Decoding

“…The first block is the sPLL, responsible of sorting the different frequencies. The structure, similar in concept to the one in [11], is composed of a Time Difference Encoder (TDE) [17]- [20] and a Current Controlled Oscillator (CCO). These two elements are closed in a negative loop, like in Figure 3.…”