An event-driven approach to crosstalk noise analysis [digital ICs]

Bazargan-Sabet, Pirouz; Renault, Patricia

doi:10.1109/simsym.2003.1192829

Cited by 2 publications

References 9 publications

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Floorplan-based crosstalk estimation for macrocell-based designs

Gupta

Katkoori

Sankaran

18th International Conference on VLSI Design Held Jointly With 4th International Conference on Embedded Systems Design

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We propose an estimation technique to measure the crosstalk susceptibility of different nets in the post global routing phase, prior to detailed routing of designs. Global routing provides the approximate routes of the wires. This is used to compute the aggressors of a given victim wire along its route and its crosstalk susceptibility with respect to those aggressors. The crosstalk susceptibility of a victim wire is given by (1) P t , the probability of crosstalk occurrence on the wire in different regions along its route; and (2) V peak , the worst case noise amplitude experienced by the wire along its route. P t is estimated using a very fast and accurate statistical estimator previously proposed by the authors. V peak is estimated by predicting the cross-coupling capacitances between neighboring wires, using their global routing information. Placement and global routing are done using CADENCE Silicon Ensemble. The predicted crosstalk estimates are compared against those by detailed HSPICE simulations. Average errors are found to be less than 8% while the execution times are significantly reduced.

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