An event‐driven model of fractional‐N CPPLLbasedFMCWsynthesizers

Abstract

This paper proposes an improved event‐driven (ED) model to improve the simulation efficiency of a mixed‐signal charge‐pump phase locked loop (CP‐PLL) design for a frequency‐modulated continuous‐wave (FMCW) chirp generation. The improvement mainly comes into three parts. First, we update the data only when it changes during the previous trigger. Second, we save the data at the triggering moment of the reference clock to achieve uniform sampling for better noise characterization. Furthermore, we propose a simplified model that is specifically optimized for the third‐order loop filter (LF). This article presents a detailed design flow of the improved ED model, and we apply it to the simulation of the FMCW chirp generation. Compared to the conventional transistor‐level simulation, our proposed model reduces the simulation time to less than 1 s, which leads to a reduction of the simulation time by five or six orders of magnitude.