An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity

Kroll, Harald; Zwicky, Stefan; Weber, Benjamin; Roth, Christoph; Benkeser, Christian; Burg, Andreas; Huang, Qiuting

doi:10.1109/esscirc.2014.6942057

Cited by 2 publications

(5 citation statements)

References 9 publications

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“…The proposed IR architecture can be incorporated into a dedicated hardware baseband processing chip from previous work [9]. The digital baseband processing ASIC presented in [11] comprises the proposed IR architecture. The latter consumes in the best case not more than 5 mW of power as opposed to 176 mW of [5].…”

Section: Discussionmentioning

confidence: 99%

“…A HDL model is implemented and synthesized using a 130 nm CMOS technology. The latter is apt for ASIC implementations such as [11].…”

Section: Contributionmentioning

confidence: 99%

“…Most notable is the required support for additional modulation schemes in DET. To this end, the SOVE algorithm as presented in [11] has been used. For an incorporation of a turbo decoder for Evolved EDGE operation the solution of [15] was taken.…”

Section: Packet Switching Technology Supportmentioning

confidence: 99%

“…Therefore, combining the two solutions would lead to 230k GE and 86 kbit of memory or, in terms of mm 2 using a 130 nm technology, 2.5 mm 2 . The proposed IR architecture has been incorporated into the 130 nm CMOS digital baseband processing ASIC presented in [11]. In the latter, the power consumption of the entire digital baseband can be as low as 5 mW.…”

Section: Synthesis and Clockingmentioning

confidence: 99%

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On the Mapping of Incremental Redundancy into a Physical Layer ASIC

Weber

Kroll

Benkeser

et al. 2014

J Sign Process Syst

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Incremental Redundancy (IR) was introduced in GSM/EDGE and later adopted in Evolved EDGE in order to keep the throughput at an acceptable level. Legacy 2G networks with their ubiquitous coverage are apt to provide a fallback solution for the latest LTE networks. On the other hand, they provide a reliable data link for emerging M2M or IoT applications. IR data processing and controlling is specified in several layers of the GSM/EDGE protocol stack. In many state-of-the-art designs this leads to decentralized data processing, and thus to costly data movements between memories and hardware accelerators. This is prohibitive for emerging M2M designs, which demand lowest possible hardware resources. In this work, IR is implemented as part of a dedicated hardware baseband signal processing unit in order to unburden higher layer processing units from IR, reduce area, power consumption, and costs. The open source baseband framework MatPHY is extended for packet switched operation to facilitate the development of efficient IR hardware architectures. With the design parameters obtained from performance evaluations computed with MatPHY an IR architecture in a 130 nm CMOS technology B. Weber ( ) •

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Section: Discussionmentioning

confidence: 99%

“…A HDL model is implemented and synthesized using a 130 nm CMOS technology. The latter is apt for ASIC implementations such as [11].…”

Section: Contributionmentioning

confidence: 99%

Section: Packet Switching Technology Supportmentioning

confidence: 99%

Section: Synthesis and Clockingmentioning

confidence: 99%

See 2 more Smart Citations

On the Mapping of Incremental Redundancy into a Physical Layer ASIC

Weber

Kroll

Benkeser

et al. 2014

J Sign Process Syst

Self Cite

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“…In this work, the single-antenna testbed of [18] which is shown in Fig. 11 has been extended to support Rx-diversity operation.…”

Section: A Measurement and Testbed Setupmentioning

confidence: 99%

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

Kroll

Zwicky

Weber

et al. 2015

IEEE J. Solid-State Circuits

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In this paper, a baseband ASIC which supports receive diversity and soft-output Viterbi equalization for enhanced 2G networks is presented. It includes a transmitter and receiver with a symbol detector and a decoder with a dedicated incremental redundancy implementation, as well as the necessary control capability to autonomously communicate with the RF-IC. The ASIC is connected to an RF-IC to build a complete Evolved EDGE transceiver system. The transceiver system reaches a measured sensitivity close to 112 dBm for single-antenna GSM voice channels and achieves the reference interference performance for adjacent channels 11.4 dB above 3GPP requirements. It is the first reported solution which fulfills the most demanding 3GPP Downlink Advanced Receive Performance Phase 2 testcases specified for Rx-diversity. The ASIC occupies 6 mm in 130 nm CMOS with a power consumption between 3.9 and 14 mW.Index Terms-Baseband ASIC, enhanced 2G networks, evolved EDGE (E-EDGE), evolved EDGE testbed, GSM/EDGE, hybrid ARQ, incremental redundancy, interference cancellation, internet of things (IoT), machine-to-machine (M2M), Rx diversity, space-time processing.

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An evolved EDGE PHY ASIC supporting soft-output equalization and Rx diversity

Cited by 2 publications

References 9 publications

On the Mapping of Incremental Redundancy into a Physical Layer ASIC

On the Mapping of Incremental Redundancy into a Physical Layer ASIC

An Evolved GSM/EDGE Baseband ASIC Supporting Rx Diversity

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