An Experimental Study of N-Detect Scan ATPG Patterns on a Processor

Venkataraman, S.; Sivaraj, S.; Amyeen, Enamul; Lee, Sang Bong; Ojha, Aparajita; Guo, Ruifeng

doi:10.1109/vtest.2004.1299221

Cited by 59 publications

(17 citation statements)

References 13 publications

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“…This method was proposed in [11], and since then it has been identified as a very effective test strategy [1]- [6], [8]- [10], [13]- [17]. The main idea of N-detect testing is to apply N (N > 1) different test patterns for each stuck-at fault.…”

Section: Introduction *mentioning

confidence: 99%

Generation of compact test sets with high defect coverage

Kavousianos

Chakrabarty

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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Abstract-Multi-detect (N-detect) testing suffers from the drawback that its test length grows linearly with N. We present a new method to generate compact test sets that provide high defect coverage. The proposed technique makes judicious use of a new pattern-quality metric based on the concept of output deviations. We select the most effective patterns from a large N-detect pattern repository, and guarantee a small test set as well as complete stuck-at coverage. Simulation results for benchmark circuits show that with a compact, 1-detect stuck-at test set, the proposed method provides considerably higher transition-fault coverage and coverage ramp-up compared to another recently-published method. Moreover, in all cases, the proposed method either outperforms or is as effective as the competing approach in terms of bridging-fault coverage and the surrogate BCE+ metric. In many cases, higher transition-fault coverage is obtained than much larger N-detect test sets for several values of N. Finally, our results provide the insight that, instead of using N-detect testing with as large N as possible, it is more efficient to combine the output deviations metric with multi-detect testing to get highquality, compact test sets.

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Section: Introduction *mentioning

confidence: 99%

Generation of compact test sets with high defect coverage

Kavousianos

Chakrabarty

2009

2009 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition

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“…Instead, a different approach should be taken to minimize the risk of test escapes while avoiding increasing test complexity. The use of N-detect appears as a valid option for this purpose [31], [32]. As this strategy excites the same fault multiple times by generating different neighboring excitations, it should increase the probability of inducing at least one proper configuration to detect the SOF.…”

Section: Test Recommendationsmentioning

confidence: 99%

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

Arumí

Rodríguez-Montañés

Figueras

2016

IEEE Trans. VLSI Syst.

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Abstract-Intragate open defects are responsible for a significant percentage of defects in present technologies. A majority of these defects causes the logic gate to become stuck open, and this is why they are traditionally modeled as stuck-open faults (SOFs). The classical approach to detect the SOFs is based on a two-vector sequence, and has been proved effective for a wide range of technologies. However, factors typically neglected in past technologies have become a major concern in nanometer technologies, i.e., leakage currents and downstream parasitic capacitances. Some recent works have examined the influence of leakage currents. However, to the best of our knowledge, no one has considered the influence of downstream parasitic capacitances. In this paper, the influence of both factors is investigated and experimentally measured with a test chip built on a 65-nm technology. An analysis based on the electrical simulations is performed to quantify the number of test escapes in the presence of SOFs. Test recommendations are derived from the analysis results to maximize the detectability of these faults in present and future technologies.

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“…This required between 5 to 8 complete test sets from the ATPG. The industrial methods mentioned in earlier papers [2,3,12,22] can also be used to generate a similar test set for further minimization.…”

Section: Single-detect Testsmentioning

confidence: 99%

“…N -detect tests are of interest because they are found to be useful in improving the defect coverage [2,3,8,18,22]. Therefore, various test generation strategies have been developed [2,14,16,19,22] to derive and apply such tests. The main disadvantage of the N -detect tests is their size.…”

Section: Introductionmentioning

confidence: 99%

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A Reduced Complexity Algorithm for Minimizing N-Detect Tests

Kantipudi

Agrawal

2007

20th International Conference on VLSI Design Held Jointly With 6th International Conference on Embedded Systems (VLSID'07)

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-We give a new recursive rounding linear programming (LP) solution to the problem of N -detect test minimzation. This is a polynomialtime solution that closely approximates the exact but NP-hard integer linear programming (ILP) solution. In ILP, a test is represented by a [0, 1] integer variable and the sum of those variables is minimized. Constraints ensure that each fault has at least N tests with non-zero variables. Traditionally, the problem has been transformed to less complex LP by treating the variables as real numbers, regarded as probabilities with which they can be rounded off to 0 or 1. This is known as the randomized rounding method. In the new method, the LP is recursively used, each time rounding the largest variable to 1 and reducing the size of the LP. The method is found to converge to a solution in just a few LP runs and the result is usually better than that of randomized rounding. Experimental results include ISCAS85 benchmarks and a set of multiplier circuits. N -detect tests for N = 1, 5 and 15 are considered. Also, a 10-vector single-detect sequence for c6288 is given.

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An Experimental Study of N-Detect Scan ATPG Patterns on a Processor

Cited by 59 publications

References 13 publications

Generation of compact test sets with high defect coverage

Generation of compact test sets with high defect coverage

Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents

A Reduced Complexity Algorithm for Minimizing N-Detect Tests

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