An Explicit Physics-Based I-V Model for Surrounding-Gate Polysilicon Transistors

Yu, Fangyong; Deng, Wanling; Huang, Junkai; Ma, Xiaoyu; Chen, Songlin

doi:10.1109/ted.2015.2512851

Cited by 16 publications

(6 citation statements)

References 26 publications

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“…To derive electrostatic potential, we use Debye length term and well-known mathematical solution z = A − 2 ln Br 2 + 1 , where A and B are constant . As a result, the electrostatic potential function can be expressed as [11,12]:…”

Section: Electrostatic Potential Modelingmentioning

confidence: 99%

“…Due to the difference in the current derivation method and approximation, there is a difference between the second term of Equation (19) and the current Equation in [11]. To calculate Q t , we should calculate…”

Section: Drain Current Modelingmentioning

confidence: 99%

“…However, there is only one published paper considering cylindrical coordinates and grain boundary effect. In Fei Yu's studies [11], which modeled the I-V characteristics through the Lambert-W function and some approximation techniques, the surface potential of poly-silicon GAA transistors have been studied. However, the result of the model is not intuitive to implement SPICE simulation because of the complexity of the Equation and to understand the device operation and major electrical characteristics (e.g.…”

Section: Introductionmentioning

confidence: 99%

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Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

Seon

Kim

et al. 2019

Electronics

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Poly-crystalline silicon channel transistors have been used as a display TFT for a long time and have recently been used in a 3D vertical NAND Flash which is a transistor with 2D plane NAND upright. In addition, multi-gate transistors such as FinFETs and a gate-all-around (GAA) structure has been used to suppress the short-channel effects for logic/analog and memory applications. Compact models for poly-crystalline silicon (poly-silicon) channel planar TFTs and single crystalline silicon channel GAA MOSFETs have been developed separately, however, there are few models consider these two physics at the same time. In this work, we derived new analytical current-voltage model for GAA transistor with poly-silicon channel by considering the cylindrical coordinates and the grain boundary effect. Based on the derived formula, the compact I-V model for various operating regions and threshold voltage was proposed for the first time. The proposed model was compared with the measured data and good agreements were observed.

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Section: Electrostatic Potential Modelingmentioning

confidence: 99%

Section: Drain Current Modelingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

Seon

Kim

et al. 2019

Electronics

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“…Here, λ is the bulk factor with λ = 2qε si n 0 /V t C 2 ox , D can be considered as the impact fact describing the B-S potential coupling effect in FD SG SOI MOSFETs with D = sin 2 β + N a cos 2 βln(sec 2 β)/4n 0 L 2 D β 2 , and ω is the Schroder series [24] used to improve the accuracy of the explicit solution of ϕ s with ω = −(y/y )/(1 − 0.5yy /y /y ). Here,…”

Section: Surface Potential Explicit Calculation Schemementioning

confidence: 99%

A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

Huang

et al. 2019

Electronics

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A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal's experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10 −7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal's experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations.

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“…Cylindrical gate MOSFET (CG-MOS) is one of the impending models which provide superior gate controllability as compared to single-gate and other multi-gate structures [6][7][8][9][10][11]. It also overcomes the physical scaling limit of conventional CMOS technology because of its typical natural length.…”

Section: Introductionmentioning

confidence: 99%

Effect of underlap length variation on DC/RF performance of dual material cylindrical MOS

Jena

Dash

Mishra

2016

Int J Numerical Modelling

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Summary Significant down‐scaling of device dimension has made cylindrical gate MOSFET (CG‐MOS), a cutting edge device for low power applications. But in order to sustain the competition for real‐time devices, it should have improved RF performances as well. In this paper, an analytical model of dual material cylindrical gate MOSFET (DMCG‐MOS) with underlap engineering has been developed using the solution of 2‐D Poisson's equation. The electrical parameters such as surface potential, threshold voltage and drain current are determined and compared with that of conventional CG‐MOS. The effect of the variation of underlap length on the DC/RF performance of the model has been extensively discussed. The results show improvement in the performance of threshold voltage, leakage current and transconductance generation factor (TGF) with the introduction of underlap at the drain end. On the contrary, the model with source underlap exhibits better drain current and higher cut‐off frequency. The analytical results are validated using Sentaurus TCAD device simulator. The improvement in DC and RF performance of this model would address emerging challenges posed by high frequency and low power applications. Copyright © 2016 John Wiley & Sons, Ltd.

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An Explicit Physics-Based I-V Model for Surrounding-Gate Polysilicon Transistors

Cited by 16 publications

References 26 publications

Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

Analytical Current-Voltage Model for Gate-All-Around Transistor with Poly-Crystalline Silicon Channel

A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

Effect of underlap length variation on DC/RF performance of dual material cylindrical MOS

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