An Extensible SAT-solver

Eén, Niklas; Sörensson, Niklas

doi:10.1007/978-3-540-24605-3_37

Cited by 1,884 publications

(1,513 citation statements)

References 7 publications

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“…The temporary constraints can be removed from the solver, automatically also removing all the constraints that the solver has learned based on those. The incremental SAT solvers currently supported by the interface are MiniSat [25] and ZChaff [26]. In the experiments we use the latest version 2004.11.15 of ZChaff as the SAT solver.…”

Section: Methodsmentioning

confidence: 99%

Incremental and Complete Bounded Model Checking for Full PLTL

Heljanko¹,

Junttila²,

Latvala³

2005

Computer Aided Verification

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Abstract. Bounded model checking is an efficient method for finding bugs in system designs. The major drawback of the basic method is that it cannot prove properties, only disprove them. Recently, some progress has been made towards proving properties of LTL. We present an incremental and complete bounded model checking method for the full linear temporal logic with past (PLTL). Compared to previous works, our method both improves and extends current results in many ways: (i) our encoding is incremental, resulting in improvements in performance, (ii) we can prove non-existence of a counterexample at shallower depths in many cases, and (iii) we support full PLTL. We have implemented our method in the NuSMV2 model checker and report encouraging experimental results.

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Section: Methodsmentioning

confidence: 99%

Incremental and Complete Bounded Model Checking for Full PLTL

Heljanko¹,

Junttila²,

Latvala³

2005

Computer Aided Verification

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“…The performance of recent complete algorithms [14]- [16] has been significantly improved by introducing several techniques to prune the search space [14]- [17]. However, these techniques also require complicated control structure, which makes it difficult to handle large real-world problems in hardware solvers.…”

Section: Related Workmentioning

confidence: 99%

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

Kanazawa

Matsumoto

2017

IEICE Trans. Inf. & Syst.

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SUMMARYWalkSAT (WSAT) is one of the best performing stochastic local search algorithms for the Boolean Satisfiability (SAT) and the Maximum Boolean Satisfiability (MaxSAT). WSAT is very suitable for hardware acceleration because of its high inherent parallelism. Formal verification of digital circuits is one of the most important applications of SAT and MaxSAT. Structural knowledge such as logic gates and their dependencies can be derived from SAT/MaxSAT instances generated from formal verification of digital circuits. Such that knowledge is useful to solve these instances efficiently. In this paper, we first discuss a heuristic to utilize the structural knowledge for solving these problems by using WSAT. Then, we show its implementation on FPGA. The problem size of the formal verification is typically very large, and most data have to be placed in offchip DRAMs. In this situation, the acceleration by FPGA is limited by the throughput and access latency of the DRAMs. In our implementation, data are carefully mapped on the on-chip memory banks and off-chip DRAMs so that most data in the off-chip DRAMs can be continuously accessed using burst-read. Furthermore, a variable-way cache memory comprised of the on-chip memory banks is used in order to hide the DRAM access latency by caching the head portion of the continuous read from the DRAMs and giving them to the circuit till the rest portion is started to be given by the burst-read. We evaluate the performance of our proposed method by changing configuration of the variable-way cache and the processing parallelism, and discuss how much acceleration can be achieved.

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“…Different methods have been applied to solve ISAT, among them, variations of the branch and bounds procedure, denoted as IDPL methods, which are usually based in the classical Davis-Putnam-Loveland (DPL) method. In a IDPL procedure, when adding new clauses, the procedure maintains the search tree generated previously for the set of clauses K. Rather than solving related formulas separately, modern solvers attempt to solve them incrementally since many practical applications require solving a sequence of related SAT formulas [3], [4].…”

Section: Incremental Satisfiability Problemmentioning

confidence: 99%

“…Rather than solving related formulas separately, modern solvers attempt to solve them incrementally, since many practical applications require solving a sequence of related SAT formulas [3], [4]. In this article, we consider ISAT as an incremental problem that starts with an initial satisfiable formula K=F in 2-CNF.…”

Section: Introductionmentioning

confidence: 99%

A Note for the Two Incremental Satisﬁability Problem

R.¹,

L.²,

L.³

2017

IJCTE

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Abstract-Let K be a two conjunctive normal form and φ a three conjunctive normal form, both formulas are defined over the same set of variables. It is well known that SAT(K) is in the complexity class P, while SAT(φ) is a classic NP-Complete problem. We consider the computational complexity of determining SAT(K φ ) as an incremental satisfiability problem (2-ISAT). We show that this problem is NP-complete even if the number of occurrences of each variable in φ is one.Also, we propose a method to review SAT(Kφ ). Our proposal is adequate to solve 2-ISAT problem. Our algorithm allows us to recognize tractable instances of 2-ISAT.

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An Extensible SAT-solver

Cited by 1,884 publications

References 7 publications

Incremental and Complete Bounded Model Checking for Full PLTL

Incremental and Complete Bounded Model Checking for Full PLTL

An Approach for Solving SAT/MaxSAT-Encoded Formal Verification Problems on FPGA

A Note for the Two Incremental Satisﬁability Problem

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