An FPGA-based all-digital transmitter with 9.6-GHz 2nd order time-interleaved delta-sigma modulation for 500-MHz bandwidth

Tanio, Masaaki; Hori, Shingo; Tawa, Noriaki; Kunihiro, Kazuaki

doi:10.1109/mwsym.2017.8058904

Cited by 20 publications

(10 citation statements)

References 4 publications

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“…In [7] and [8], samples are deinterleaved into multiple blocks and processed by multicore DSMs in parallel, leading to increased memory usage and latency. In [6], good performance has been achieved using a bit separation architecture where all possible internal states of the high-order bits calculation were stored in memory. It is, however, unclear how much the performance is compromised by reducing the internal states.…”

Section: Experimental Verificationmentioning

confidence: 99%

“…ASIC or FPGA), since it involves several high-precision additions in a single clock cycle. As a result, most prior works rely on time-interleaved DSMs (TI DSMs) for the implementation of a high-speed DSM [3]- [6]. However, the loop-unrolled architectures in TI DSM are eventually limited by the critical path (CP).…”

Section: Introductionmentioning

confidence: 99%

“…However, the loop-unrolled architectures in TI DSM are eventually limited by the critical path (CP). In [6], a bit separation architecture was proposed to increase the sampling rate where all possible internal states of the high-order bit calculation (where the feedback path exists) were stored in memory. [7] and [8] proposed a highspeed parallel DSM architecture using multicore DSMs, where samples were sliced into multiple blocks and each block was processed by one DSM core.…”

Section: Introductionmentioning

confidence: 99%

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A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs

Breyne

Kerrebrouck

et al. 2019

IEEE Trans. Circuits Syst. II

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A new high-speed delta-sigma modulator (DSM) topology is proposed by cascading a bit reduction process with a multi-stage noise shaping MASH-1-1 DSM. This process converts the two-bit output sequence of the MASH-1-1 DSM to a singlebit sequence, merely compromising the DSM noise-shaping performance. Furthermore, the high clock frequency requirements are significantly relaxed by using parallel processing. This DSM topology facilitates the design of e.g. wideband software defined radio (SDR) transmitters and delta-sigma radio-over-fiber transmitters. Experimental results of the FPGA implementation show that the proposed low-pass DSM can operate at 21 GS/s, providing 520 MHz baseband bandwidth with 42.76 dB signal-to-noiseand-distortion ratio (SNDR) or 1.1 GHz bandwidth with 32.04 dB SNDR (based on continuous wave measurements). An all-digital transmitter based on this topology can generate 218.75 MBd 256-QAM over 200 m OM4 multimode fiber in real-time, with 7-GS/s sampling rate and an error vector magnitude below 1.89%.

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Section: Experimental Verificationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs

Breyne

Kerrebrouck

et al. 2019

IEEE Trans. Circuits Syst. II

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“…2 AWG: arbitrary waveform generator. 3 The performance of references [30]- [48] are illustrated in Fig. 1.…”

mentioning

confidence: 99%

“…As a cornerstone of SDR, all-digital RF transceiver based on delta-sigma modulation has attracted intensive research interest due to its low cost and flexibility to accommodate multiband multi-RAT operations. Both transmitter [30]- [52] and receiver [53]- [59] designs have been reported, and various delta-sigma modulators, including lowpass [30], [32]- [34], [36]- [39], [41]- [45], [47], [48], bandpass [31], [35], and multiband [40], [49]- [52] have been demonstrated. To relax the FPGA speed requirement, several time-interleaving or parallel processing techniques are also presented [38], [39], [43]- [45], [47], [48].…”

mentioning

confidence: 99%

Delta-Sigma Modulation for Next Generation Fronthaul Interface

Wang

Jia

Campos

et al. 2019

J. Lightwave Technol.

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A new function split option for the next generation fronthaul interface (NGFI) is demonstrated based on all-digital RF transmitter using bandpass delta-sigma modulation. Different from other low layer split (LLS) options, such as option 6 (MAC-PHY), 7 (high-low PHY), and 8 (CPRI), the proposed option 9 implements RF functions in the digital domain, and splits within the RF layer, with high-RF layer centralized in the distributed unit (DU) and low-RF layer distributed in remote radio units (RRUs). A proof-of-concept all-digital RF transmitter based on real-time delta-sigma modulation is implemented using a Xilinx Virtex-7 FPGA. A 5-GSa/s delta-sigma modulator is demonstrated to encode LTE/5G signals with bandwidth up to 252 MHz and modulation format up to 1024-QAM to a 5-Gb/s OOK signal, which is transmitted over 30-km single-mode fiber from DU to RRU. To relax the FPGA speed requirement, a 32-pipeline architecture is designed. Two-carrier aggregation of 5G and 14-carrier aggregation of LTE signals are demonstrated with error vector magnitude (EVM) performance satisfying the 3GPP specifications. Compared with option 8 (CPRI), although the proposed option 9 split occurs at a lower level, it offers improved spectral efficiency and reduced NGFI data rate than CPRI. Moreover, other LLS options, such as 6, 7, and 8, all require a complete RF layer implemented in the analog domain at remote cell sites; whereas option 9 realizes high-RF layer in the digital domain at DU, and eliminates the need of analog RF devices, such as DAC, local oscillator and mixer at RRU, which not only makes low-cost, energy-efficient, and small-footprint cell sites possible for the wide deployment of small cells, but also paves the road toward software defined radio (SDR) and virtualization of DU and RRU for improved compatibility and reconfigurability among multiple radio access technologies (multi-RATs). Given its centralized architecture and deterministic latency, option 9 is suitable for radio coordination applications, and has potential in low-frequency narrowband scenarios with cost, power, and/or size sensitive cell sites, such as massive machine type communication (mMTC) and narrowband internet of things (NB-IoT). Index Terms-All-digital RF transmitter, delta-sigma modulation, fronthaul, NGFI, software defined radio. I. INTRODUCTION T HE emerging video-intensive and bandwidth-consuming services, e.g., virtual reality, augmented reality, immersive applications, are driving the explosive growth of mobile data traffic [1]-[3], making radio access networks (RAN) become

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Highly compact GaN-based all-digital transmitter chain including SPDT T/Rx switch for massive MIMO applications

Huhn

Wentzel

Heinrich

2019

Int. J. Microw. Wireless Technol.

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This paper presents a fully digital transmitter chain from baseband to antenna, including a modulator, two truly digital (i.e. fully switched) microwave power amplifiers and a transmit/receive switch. Both, amplifier and switch monolithic microwave integrated circuits were implemented in a GaN HEMT process. The novel amplifier design provides greatly reduced complexity, needing only three voltage sources. Measurements were conducted using 5, 20, and 100 MHz wide baseband signals. Carrier frequencies cover the 900 and 2000 MHz bands. For the 5 MHz BB signal an ACLR of over 52 dB is reached, fulfilling the 3GPP specs for base station use while still maintaining a final-stage drain efficiency of 46% at 6.5 dB peak to average power ratio. Full-scale output power at 30 V supply voltage was measured to exceed 3 W at 80% drain efficiency. Further features of this digital amplifier approach include small form factor and frequency agility, making it an ideal candidate for software defined radio.

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An FPGA-based all-digital transmitter with 9.6-GHz 2nd order time-interleaved delta-sigma modulation for 500-MHz bandwidth

Cited by 20 publications

References 4 publications

A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs

A 21-GS/s Single-Bit Second-Order Delta–Sigma Modulator for FPGAs

Delta-Sigma Modulation for Next Generation Fronthaul Interface

Highly compact GaN-based all-digital transmitter chain including SPDT T/Rx switch for massive MIMO applications

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