2016 IEEE MTT-S International Microwave Symposium (IMS) 2016
DOI: 10.1109/mwsym.2016.7540142
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An FPGA-based all-digital transmitter with 28-GHz time-interleaved delta-sigma modulation

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Cited by 16 publications
(9 citation statements)
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“…The needed complex zero can be obtained by simply replacing the coefficients r and c from (5) with the values corresponding to the targeted normalized frequency (fn), which can be obtained using the relationship between the z-transform and the Fourier transform in (6). (6) where A is the modulus of the complex number z.…”
Section: A General Architecture Of 1 St Order Cdsmmentioning
confidence: 99%
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“…The needed complex zero can be obtained by simply replacing the coefficients r and c from (5) with the values corresponding to the targeted normalized frequency (fn), which can be obtained using the relationship between the z-transform and the Fourier transform in (6). (6) where A is the modulus of the complex number z.…”
Section: A General Architecture Of 1 St Order Cdsmmentioning
confidence: 99%
“…Therefore, using this CDSM scheme, the denominator from (7-8) is reduced to a simple delay z -1 (independent of r and c, no complex coefficients), whereas the numerator in (8) remains identical to (5) and enables the placement of the custom complex zero according to (6).…”
Section: B Proposed 1 St Order Cdsmmentioning
confidence: 99%
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“…As a cornerstone of SDR, all-digital RF transceiver based on delta-sigma modulation has attracted intensive research interest due to its low cost and flexibility to accommodate multiband multi-RAT operations. Both transmitter [30]- [52] and receiver [53]- [59] designs have been reported, and various delta-sigma modulators, including lowpass [30], [32]- [34], [36]- [39], [41]- [45], [47], [48], bandpass [31], [35], and multiband [40], [49]- [52] have been demonstrated. To relax the FPGA speed requirement, several time-interleaving or parallel processing techniques are also presented [38], [39], [43]- [45], [47], [48].…”
mentioning
confidence: 99%