An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices

Mohsin, Mokhles A.; Perera, Darshika G.

doi:10.1145/3241793.3241810

Cited by 25 publications

(17 citation statements)

References 4 publications

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“…Hence, it can be said that the comparisons were appropriate. This is an advantage of the FPGA-based prototype design [42] [43]. In addition, the capability to analyze the specifications of customized processors (e.g., the customized DSP and CPU analyzed in this study) is another advantage of the FPGA-based prototype design.…”

Section: ) Discussionmentioning

confidence: 99%

A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot

Takeda

Torikai

2020

IEEE Access

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This paper presents a novel hardware-efficient central pattern generator (CPG) model to realize a bio-inspired gait of a hexapod robot. The CPG model consists of a network of cellular automaton (CA) oscillators; thus, it can be implemented as a network of sequential logic circuits. Detailed analyses of nonlinear oscillation dynamics show that the oscillator that is driven by multiple asynchronous clocks is more suitable to realize the gait of the robot than an oscillator that is driven by a single clock or multiple synchronous clocks. Moreover, detailed analyses of nonlinear network dynamics show that the clocks among the CA oscillators should be asynchronous to appropriately realize the gait. Using the analyses, systematic procedures to design the CPG model are proposed. The proposed CPG model is implemented in a field programmable gate array (FPGA); our experiments validate that the CPG model implemented in an FPGA can realize the bio-inspired gait of a hardware robot. Further, we show that the proposed CPG model utilizes fewer circuit elements and lower power than a conventional CPG model. INDEX TERMS Asynchronous Cellular Automaton. Central Pattern Generator (CPG). Field Programmable Gate Array (FPGA). Hexapod Robot. Nonlinear dynamics. Synchronization.

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Section: ) Discussionmentioning

confidence: 99%

A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot

Takeda

Torikai

2020

IEEE Access

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“…Previous hardware implementations of the kNN classifier targeting FPGAs and SoCs have been proposed (e.g., [8], [10], [12], [13], [15]- [18]). However, such proposals tackle particular applications of kNN, adopt custom fixed-point representations, and, in general, need to be re-engineered whenever the parameters of the classifier or the dataset change.…”

Section: Related Workmentioning

confidence: 99%

“…However, in the particular context of the kNN algorithm, designing a dedicated accelerator is not trivial due to the constant change of the datasets' parameters, the classifier requirements and how data is fed to the system. Previous work on kNN accelerators targeting Field-Programmable Gate Arrays (FPGAs) and SoCs often do not scale in terms of performance and hardware and energy requirements and support only a small set of devices [8]- [12]. Furthermore, they require to re-implement the designs whenever changing the parameters of the dataset.…”

Section: Introductionmentioning

confidence: 99%

kNN-STUFF: kNN STreaming Unit for Fpgas

2019

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This paper presents kNN STreaming Unit For Fpgas (kNN-STUFF), a modular, scalable and efficient Hardware/Software implementation of k-Nearest Neighbors (kNN) classifier targeting System on Chip (SoC) devices. It takes advantage of custom accelerators, implemented on the reconfigurable fabric of the SoC device, to perform most of the classifier's workload, whereas the processor coordinates the accelerators and runs the remaining workload of the kNN algorithm. kNN-STUFF offers a highly flexible framework, where the designer has the possibility to define the number of parallel instances of the classifier and the parallelism within each instance. This capability allows creating the most suitable implementation for a target device of any size. Results show that kNN-STUFF, with 24 accelerators, attains performance improvements up to 67.4×, when compared to an optimized (-O3) software-only implementation of the kNN running on a single core of the ARM Cortex-A9 CPU. Furthermore, its energy efficiency improvements are as high as 50.6×.

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“…Our previous work [15], [16], [17] and analyses [18] illustrated that Field Programmable Gate Array (FPGA) based systems are currently the best avenue to support compute/data-intensive applications/algorithms running on resource-constrained embedded devices. This is mainly because FPGAs comprise many attractive features that are beneficial to support applications/algorithms on embedded devices.…”

Section: Introductionmentioning

confidence: 99%

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

Alkamil

Perera

2020

IEEE Access

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An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification for Machine Learning on Mobile Devices

Cited by 25 publications

References 4 publications

A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot

A Novel Hardware-Efficient Central Pattern Generator Model Based on Asynchronous Cellular Automaton Dynamics for Controlling Hexapod Robot

kNN-STUFF: kNN STreaming Unit for Fpgas

Towards Dynamic and Partial Reconfigurable Hardware Architectures for Cryptographic Algorithms on Embedded Devices

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