An FPGA-based in-line accelerator for Memcached

Lavasani, Maysam; Angepat, Hari; Chiou, Derek

doi:10.1109/hotchips.2013.7478313

Cited by 10 publications

(6 citation statements)

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“…Research efforts [14,15,28,32] in this direction achieve up to 13.2MRPS [14] with a 10GbE link and more than 10X improvements on energy efficiency compared to commodity servers running stock memcached. There are also non-FPGA-based architecture proposals [20,30,33,37] for accelerating memcached and/or improving performance and efficiency of various datacenter workloads.…”

Section: Background and Related Workmentioning

confidence: 99%

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Lim

Lee

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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Distributed in-memory key-value stores (KVSs), such as memcached, have become a critical data serving layer in modern Internet-oriented datacenter infrastructure. Their performance and efficiency directly affect the QoS of web services and the efficiency of datacenters. Traditionally, these systems have had significant overheads from inefficient network processing, OS kernel involvement, and concurrency control. Two recent research thrusts have focused upon improving key-value performance. Hardware-centric research has started to explore specialized platforms including FPGAs for KVSs; results demonstrated an order of magnitude increase in throughput and energy efficiency over stock memcached. Software-centric research revisited the KVS application to address fundamental software bottlenecks and to exploit the full potential of modern commodity hardware; these efforts too showed orders of magnitude improvement over stock memcached.We aim at architecting high performance and efficient KVS platforms, and start with a rigorous architectural characterization across system stacks over a collection of representative KVS implementations. Our detailed full-system characterization not only identifies the critical hardware/software ingredients for high-performance KVS systems, but also leads to guided optimizations atop a recent design to achieve a recordsetting throughput of 120 million requests per second (MRPS) on a single commodity server. Our implementation delivers 9.2X the performance (RPS) and 2.8X the system energy efficiency (RPS/watt) of the best-published FPGA-based claims. We craft a set of design principles for future platform architectures, and via detailed simulations demonstrate the capability of achieving a billion RPS with a single server constructed following our principles.

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Section: Background and Related Workmentioning

confidence: 99%

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Lim

Lee

et al. 2015

Proceedings of the 42nd Annual International Symposium on Computer Architecture

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show abstract

“…However, efficiently managing a TLB shared by many parallel processing elements (PEs) and notifying individual PE with low latency about handled misses is not trivial. For this reason, current hybrid SVM solutions [8], [6] only feature a single PTW thread. In this work, we show how to efficiently manage a shared TLB with multiple software PTW threads.…”

Section: Related Workmentioning

confidence: 99%

“…It is comprised of a translation lookaside buffer (TLB), parallel hardware page table walkers (PTWs), transaction and data buffers, and coherent page table caches. The alternative is a hybrid hardware-software design, which consists of a TLB controlled by software (e.g., by a kernel driver on the host [6], [7] or directly by the accelerator [8]). We subsequently refer to the former class of IOMMUs as conventional and to the second class as hybrid.…”

Section: Introductionmentioning

confidence: 99%

Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine

Kurth

Vogel

Marongiu

et al. 2018

2018 IEEE 36th International Conference on Computer Design (ICCD)

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Shared virtual memory (SVM) is key in heterogeneous systems on chip (SoCs), which combine a generalpurpose host processor with a many-core accelerator, both for programmability and to avoid data duplication. However, SVM can bring a significant run time overhead when translation lookaside buffer (TLB) entries are missing. Moreover, allowing DMA burst transfers to write SVM traditionally requires buffers to absorb transfers that miss in the TLB. These buffers have to be overprovisioned for the maximum burst size, wasting precious on-chip memory, and stall all SVM accesses once they are full, hampering the scalability of parallel accelerators.In this work, we present our SVM solution that avoids the majority of TLB misses with prefetching, supports parallel burst DMA transfers without additional buffers, and can be scaled with the workload and number of parallel processors. Our solution is based on three novel concepts: To minimize the rate of TLB misses, the TLB is proactively filled by compiler-generated Prefetching Helper Threads, which use run-time information to issue timely prefetches. To reduce the latency of TLB misses, misses are handled by a variable number of parallel Miss Handling Helper Threads. To support parallel burst DMA transfers to SVM without additional buffers, we add lightweight hardware to a standard DMA engine to detect and react to TLB misses. Compared to the state of the art, our work improves accelerator performance for memory-intensive kernels by up to 4× and by up to 60 % for irregular and regular memory access patterns, respectively.

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“…The hardware-based approach uses specialized platforms such as FPGAs. Research efforts [14,15,28,32] in this direction achieve up to 13.2MRPS [14] with a 10GbE link and more than 10X improvements on energy efficiency compared to commodity servers running stock memcached. There are also non-FPGA-based architecture proposals [20,30,33,37] for accelerating memcached and/or improving performance and efficiency of various datacenter workloads.…”

Section: Background and Related Workmentioning

confidence: 99%

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Lim

Lee

et al. 2015

SIGARCH Comput. Archit. News

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An FPGA-based in-line accelerator for Memcached

Cited by 10 publications

References 0 publications

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

Scalable and Efficient Virtual Memory Sharing in Heterogeneous SoCs with TLB Prefetching and MMU-Aware DMA Engine

Architecting to achieve a billion requests per second throughput on a single key-value store server platform

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