2017 IEEE Aerospace Conference 2017
DOI: 10.1109/aero.2017.7943634
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An FPGA-based radiation tolerant SmallSat Computer System

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Cited by 11 publications
(8 citation statements)
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“…This means that the proposed control introduced in the terminal descent phase is essential and very effective and makes the landing very precise and reliable. For this terminal descent phase, the mass consumption varies within the range [1.20, 2.94] kg in the case of ∆t P = 1 s and [1.20, 3.08] kg in the case of ∆t P = 2 s. Thus, the total mass consumption considering the two phases (approaching phase and terminal descent) can be considered within the range [28,39] kg. Another test is performed considering 10 successive optimizations during the approaching phase (without hazard detection and thus without updating the final position of the approaching phase).…”
Section: Numerical Resultsmentioning
confidence: 99%
See 1 more Smart Citation
“…This means that the proposed control introduced in the terminal descent phase is essential and very effective and makes the landing very precise and reliable. For this terminal descent phase, the mass consumption varies within the range [1.20, 2.94] kg in the case of ∆t P = 1 s and [1.20, 3.08] kg in the case of ∆t P = 2 s. Thus, the total mass consumption considering the two phases (approaching phase and terminal descent) can be considered within the range [28,39] kg. Another test is performed considering 10 successive optimizations during the approaching phase (without hazard detection and thus without updating the final position of the approaching phase).…”
Section: Numerical Resultsmentioning
confidence: 99%
“…This results in a more robust trajectory planning. All the work presented in this paper represents the first step for future real-time testing on hardware that has already been tested for flight, such as FPGA [28].…”
Section: Introductionmentioning
confidence: 99%
“…So far, there is no standard or common practices regarding system level data reporting, rather applicationspecific testing and reporting are done. In [3], for instance, a system level failure happens when the system generates an incorrect GPS output and non-critical or soft-error occurs when system crash or loss of positioning happens, whereas in [4], a system failure occurs when bugs are reported by a customized operational system or configuration bit upsets occur. This approach makes the component level information gathering more difficult and avoids the reusability of a system level test data.…”
Section: Motivationmentioning
confidence: 99%
“…These are called temporal faults. These unwanted bit flips are often caused by effects such as ionizing radiation and extreme temperatures [52]. [59].…”
Section: Reliability Issues In Fpgasmentioning
confidence: 99%
“…configuration bitstream in runtime especially for safety-critical applications. SRAMbased FPGA CMEM are volatile, and the bits stored in them could be flipped due to undesired effects such as radiation and extreme temperatures[52]. To mitigate the effects of unwanted bit flips, each configuration frame in the bitstream of XilinxFPGAs is protected by a Frame Error Correcting Code (Frame ECC).…”
mentioning
confidence: 99%