An FPGA-based time-domain frequency shifter with application to LTE and LTE-A systems

Figueiredo, Felipe Augusto Pereira de; Mathilde, Fabiano; Figueiredo, Fabrício L.; Cardoso, Fabbryccio A. C. M.

doi:10.1109/lascas.2015.7250408

Cited by 4 publications

(2 citation statements)

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Section: Introductionmentioning

confidence: 99%

“…This paper is an extension of a previous conference paper [8]. Differently from [8], where we provided only some very superficial aspects of the proposed algorithm and architecture, the current paper presents a meticulous analysis on its design and implementation aspects. Therefore, the main contributions of the current paper are (i) the design of a low computational complexity time-domain frequency shifter algorithm and hardwarearchitecturetobeemployedin the PRACH receiver at eNodeB side; (ii) a thorough analysis of design and implementation details; (iii) discussion of the computational complexity of the proposed architecture in terms of FPGA resource utilisation and speed; and (iv) careful analysis of the implementation results considering spur suppression, i.e.…”

Section: Introductionmentioning

confidence: 99%

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An Efficient FPGA-Based Frequency Shifter for LTE/LTE-A Systems

Figueiredo¹,

Cardoso²

2020

Field Programmable Gate Arrays (FPGAs) II

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The Physical Random Access Channel plays an important role in LTE and LTE-A systems. Through this channel, the user equipment aligns its uplink transmissions to the eNodeB's uplink and gains access to the network. One of the initial operations executed by the receiver at eNodeB side is the translation of the channel's signal back to base-band. This operation is a necessary step for preamble detection and can be executed through a time-domain frequency-shift operation. Therefore, in this paper, we present the hardware architecture and design details of an optimised and configurable FPGA-based time-domain frequency shifter. The proposed architecture is based on a customised Numerically Controlled Oscillator that is employed for creating complex exponential samples using only plain logical resources. The main advantage of the proposed architecture is that it completely removes the necessity of saving in memory a huge number of long complex exponentials by making use of a Look-Up Table and exploiting the quarter-wave symmetry of the basis waveform. The results demonstrate that the proposed architecture provides high Spurious Free Dynamic Range signals employing only a minimal number of FPGA resources. Additionally, the proposed architecture presents spur-suppression ranging from 62.13 to 153.58 dB without employing any correction.

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Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%