2017
DOI: 10.1088/1748-0221/12/12/p12019
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An FPGA based track finder for the L1 trigger of the CMS experiment at the High Luminosity LHC

Abstract: A: A new tracking detector is under development for use by the CMS experiment at the High-Luminosity LHC (HL-LHC). A crucial requirement of this upgrade is to provide the ability to reconstruct all charged particle tracks with transverse momentum above 2-3 GeV within 4 µs so they can be used in the Level-1 trigger decision. A concept for an FPGA-based track finder using a fully time-multiplexed architecture is presented, where track candidates are reconstructed using a projective binning algorithm based on the… Show more

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Cited by 39 publications
(21 citation statements)
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“…An implementation of this algorithm has been developed in FPGA firmware, and validated in hardware. This implementation of the Hough transform searches of primary tracks in the r − φ plane, using the parameter φ 0 , and the free parameter q/p T [7,8]. Stub positions in r − φ space correspond to straight lines in Hough space.…”
Section: Track Finding Algorithms and Resultsmentioning
confidence: 99%
“…An implementation of this algorithm has been developed in FPGA firmware, and validated in hardware. This implementation of the Hough transform searches of primary tracks in the r − φ plane, using the parameter φ 0 , and the free parameter q/p T [7,8]. Stub positions in r − φ space correspond to straight lines in Hough space.…”
Section: Track Finding Algorithms and Resultsmentioning
confidence: 99%
“…An intriguing proposal consists on adopting a fully time multiplexed architecture based on FPGA processing cards, similar to the one currently employed in the Stage-2 L1 Calorimeter Trigger [4], in which each event or BX is processed by a single processing unit.…”
Section: The Time Multiplexed Track Triggermentioning
confidence: 99%
“…DTCs from two neighbour detector octants timemultiplex and duplicate stubs across processing octant boundaries, before sending them to the TFPs. [4] • Geometric Processor (GP). It takes in input stubs form the DTCs and it converts them into a useful data format, to ease the load on the downstream stages.…”
Section: Pos(twepp-17)131mentioning
confidence: 99%
See 1 more Smart Citation
“…It is capable of processing the data from one octant in φ, |η| < 2.4, and one out of every thirty-six 40 MHz events (equivalent to T = 36 events). More details on the demonstrator firmware can be found in [9]. The building blocks of the hardware demonstrator are the Master Processor 7 (MP7) [10], FPGA-based, data-stream processing double-width AMC cards, equipped with a Xilinx Virtex-7 690 [11] FPGA, and 72 optical transmitters/receivers running at 10 Gbps each way.…”
Section: Demonstrator Hardware and Softwarementioning
confidence: 99%