An FPGA family optimized for high densities and reduced routing delay

Ahrens, Markus; Gamal, Abbas El; Galbraith, D.; Greene, Jonathan; Kaptanoglu, Sinan; Dharmarajan, K.R.; Hutchings, L.; Ku, Sheng-Ju; McGibney, P.; McGowan, J.; Sanie, A.; Shaw, K.; Stiawalt, N.; Whitney, Telle; Wong, Thomas G.; Wong, Wallace; Wu, Bo

doi:10.1109/cicc.1990.124844

“…We assume that the logic modules in an FPGA are identical and are laid out in regular structure dened by a rectangular grid. The symmetrical array [4,8] and row-based architectures [3,7,9] used in popular commercial FPGAs belong to such regular structures.…”

Section: Clock T Ree Architecturementioning

confidence: 99%

“…The total number and distribution of logic modules connected to a particular clock signal network in multi-phase clocks depend on circuit design and cannot be predetermined before FPGA fabrication. We t h us need to allow each individual logic module to have the freedom of selecting clock signal to connect to [1,2,3,4,9]. Another reason is that circuit designer may occasionally want to drive clock pin by the outputs of logic modules for local asynchronous clocking [1,2].…”

Section: Introductionmentioning

confidence: 99%

Clock skew minimization during FPGA placement

Zhu

¹

,

Wong

²

1994

Proceedings of the 31st Annual Conference on Design Automation Conference - DAC '94

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Unlike traditional ASIC technologies, the geometrical structures of clock trees in an FPGA are usually xed and cannot be changed for dierent circuit designs. Moreover, the clock pins are connected to the clock trees via programmable switches. As a result, the load capacitances of a clock tree may b e c hanged, depending on the utilization and distribution of logic modules in an FPGA. It is possible to minimize clock s k ew by distributing the load capacitances, or equivalently the logic modules used by the circuit design, carefully according to the circuit design. In this paper we present an algorithm for selecting logic modules used for circuit placement such that the clock s k ew is minimized. The algorithm can be applied to a variety of clock tree architectures, including those used in major commercial FPGAs. Furthermore, the algorithm can be extended to handle buered clock trees and multi-phase clock trees. Experimental results show that the algorithm can reduce clock s k ews signicantly as compared with the traditional placement algorithms which do not consider clock s k ew minimization.

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“…We assume that the logic modules in an FPGA are identical and are laid out in regular structure dened by a rectangular grid. The symmetrical array [4,8] and row-based architectures [3,7,9] used in popular commercial FPGAs belong to such regular structures.…”

Section: Clock T Ree Architecturementioning

confidence: 99%

“…The total number and distribution of logic modules connected to a particular clock signal network in multi-phase clocks depend on circuit design and cannot be predetermined before FPGA fabrication. We t h us need to allow each individual logic module to have the freedom of selecting clock signal to connect to [1,2,3,4,9]. Another reason is that circuit designer may occasionally want to drive clock pin by the outputs of logic modules for local asynchronous clocking [1,2].…”

Section: Introductionmentioning

confidence: 99%

Clock skew minimization during FPGA placement

Zhu¹,

Wong

²

1997

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Unlike traditional ASIC technologies, the geometrical structures of clock trees in an FPGA are usually xed and cannot be changed for dierent circuit designs. Moreover, the clock pins are connected to the clock trees via programmable switches. As a result, the load capacitances of a clock tree may b e c hanged, depending on the utilization and distribution of logic modules in an FPGA. It is possible to minimize clock s k ew by distributing the load capacitances, or equivalently the logic modules used by the circuit design, carefully according to the circuit design. In this paper we present an algorithm for selecting logic modules used for circuit placement such that the clock s k ew is minimized. The algorithm can be applied to a variety of clock tree architectures, including those used in major commercial FPGAs. Furthermore, the algorithm can be extended to handle buered clock trees and multi-phase clock trees. Experimental results show that the algorithm can reduce clock s k ews signicantly as compared with the traditional placement algorithms which do not consider clock s k ew minimization.

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“…2.6 [139,152], is based on a multiplexer's ability to implement various logic functions by connecting its input to either some constant value or to a signal [153]. The functionality of a LUT based FPGA is similar to distributed arithmetic (DA) where a LUT is used to implement a truth table [128].…”

Section: Basic Building Blocksmentioning

confidence: 99%

Techniques for Efficient Implementation of FIR and Particle Filtering

Alam

¹

2016

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Finite-length impulse response (FIR) filters occupy a central place many signal processing applications which either alter the shape, frequency or the sampling frequency of the signal. FIR filters are used because of their stability and possibility to have linear-phase but require a high filter order to achieve the same magnitude specifications as compared to infinite impulse response (IIR) filters. Depending on the size of the required transition bandwidth the filter order can range from tens to hundreds to even thousands. Since the implementation of the filters in digital domain requires multipliers and adders, high filter orders translate to a large number of these arithmetic units for its implementation. Research towards reducing the complexity of FIR filters has been going on for decades and the techniques used can be roughly divided into two categories; reduction in the number of multipliers and simplification of the multiplier implementation.One technique to reduce the number of multipliers is to use cascaded subfilters with lower complexity to achieve the desired specification, known as frequency-response masking (FRM). One of the sub-filters is a upsampled model filter whose band edges are an integer multiple, termed as the period L, of the target filter's band edges. Other sub-filters may include complement and masking filters which filter different parts of the spectrum to achieve the desired response. From an implementation point-of-view, time-multiplexing is beneficial because generally the allowable maximum clock frequency supported by the current state-of-the-art semiconductor technology does not correspond to the application bound sample rate. A combination of these two techniques plays a significant role towards efficient implementation of FIR filters. Part of the work presented in this dissertation is architectures for time-multiplexed FRM filters that benefit from the inherent sparsity of the periodic model filters.These time-multiplexed FRM filters not only reduce the number of multipliers but lowers the memory usage. Although the FRM technique requires a higher number delay elements, it results in fewer memories and more energy efficient memory schemes when time-multiplexed. Different memory arrangements and memory access schemes have also been discussed and compared in terms of their efficiency when using both single and dual-port memories. An efficient v vi Abstract pipelining scheme has been proposed which reduces the number of pipelining registers while achieving similar clock frequencies. The single optimal point where the number of multiplications is minimum for non-time-multiplexed FRM filters is shown to become a function of both the period, L and time-multiplexing factor, M . This means that the minimum number of multipliers does not always correspond to the minimum number of multiplications which also increases the flexibility of implementation. These filters are shown to achieve power reduction between 23% and 68% for the considered examples.To simplify the multiplier, alt...

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An FPGA family optimized for high densities and reduced routing delay

Cited by 31 publications

References 6 publications

Clock skew minimization during FPGA placement

Clock skew minimization during FPGA placement

Clock skew minimization during FPGA placement

Techniques for Efficient Implementation of FIR and Particle Filtering

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