An FPGA implementation and performance evaluation of the seed block cipher

Kitsos, Paris; Skodras, Athanassios

doi:10.1109/icdsp.2011.6004926

Cited by 4 publications

(5 citation statements)

References 5 publications

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“…It is obvious that the architectures in [20, 21] are better, in some areas than the proposed one, but their design philosophy is very different than ours (they are architectures for high‐speed applications). In [22], an architecture of Present cipher is presented for encryption‐only operation and its hardware implementation.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 95%

“…So, reliable comparisons in term of the covered area between the proposed architecture and the other previously published architectures are impossible. Table 4 gives comparisons with previously published architectures for SEED cipher [7,8], [20,21] and for Present cipher [22][23][24]. Present is part of the ISO/IEC 29192-2:2012 standard [25] that specifies lightweight block ciphers suitable for IoT.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

“…This means that the encryption rate is 4.4 Mbps. In addition, in [20], the SEED implementation is designed with a datapath equal to 128 bits and it achieves a throughput equal to 369.6 Mbps at 46.2 MHz. This implementation consumes 8268 LUTs.…”

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

See 2 more Smart Citations

8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

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This study presents an 8-bit serialised architecture of SEED block cipher for constrained devices. The circuit utilises 356 FPGA slices and 447 1-bit registers flip-flops (FFs) in the BASYS3 board, operates with an 8-bit datapath and is aimed for use on area constraints devices. In order to keep the usage of hardware resources to a minimum but, at the same time, achieve a high level of security, the key generation process of SEED is implemented through an on-the-fly procedure. In addition, the necessary S-boxes are implemented using composite field arithmetic without using any block RAMs, resulting in a very compact implementation. The proposed architecture achieves a maximum frequency equal to 125 MHz with a total latency of 280 clock cycles and a throughput up to 57.1 Mbps for encryption or decryption.

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Section: Fpga Implementation and Resultsmentioning

confidence: 95%

Section: Fpga Implementation and Resultsmentioning

confidence: 99%

See 1 more Smart Citation

8‐bit serialised architecture of SEED block cipher for constrained devices

Pirpilidis

Pyrgas

Kitsos

2020

IET Circuits, Devices & Systems

Self Cite

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show abstract

“…Chaotic functions are of important classes of random sequence generation for stream cipher system [9][10]. Some of the stream cipher algorithms based on chaotic systems and their implementations are discussed in [11][12][13][14][15].…”

Section: Introductionmentioning

confidence: 99%

Pseudo Random Binary Sequences Obtained Using Novel Chaos Based Key Stream Generator and their Auto-correlation Properties

G S,

2023

IJRITCC

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In this paper, psuedo random binary sequences are generated from the “Chaos Based Key Stream Generator- using novel Permutation technique with two dimensional patterns and substitution technique with Z4 mapping” and investigation of auto correlation property for the generated seuwnces is presented. Initially a chaotic function, considering Logistic map is used to generate a Pseudo Random Numbers (PRNs). Then these numbers are converted into binary sequences using binary mapping. These sequences are further modified by novel permutation techniques defined using 2-Dimensional patterns, and substitution technique defined over Z4 transformation in order to improve their statistical properties. The resulting sequences are investigated for auto correlation properties using Normalized Hamming Auto Correlation function. The purpose of this work is to assessing the quality of sequences of uniformly distributed pseudorandom numbers from the proposed generator. It is found that, generated sequences exhibit good auto-correlation property which is suitable for key sequence or secret key for cryptographic applications.

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“…As a device for realizing multiuser and massive data cryptographic services, the high-performance cryptographic server must achieve the following two points: First is the correctness of user services: the processing request of different users cannot be confused, and the second is the rapidity of data processing. ere are many researches on the fast implementation of the cryptographic algorithm itself, such as improving the computing performance of block cipher algorithm through pipelining [9][10][11][12][13] and optimizing the key operations of public-key cryptography algorithm to improve the operation speed [14][15][16]. Some studies also accelerate the performance of cryptographic operations through multicore parallelism.…”

Section: Related Researchmentioning

confidence: 99%

An Efficient Stream Data Processing Model for Multiuser Cryptographic Service

Shi

et al. 2018

Journal of Electrical and Computer Engineering

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In view of the demand for high-concurrency massive data encryption and decryption application services in the security field, this paper proposes a dual-channel pipeline parallel data processing model (DPP) according to the characteristics of cryptographic operations and realized cryptographic operations of cross-data streams with different service requirements in a multiuser environment. By encapsulating cryptographic operation requirements in job packages, the input data flow is divided by the dualchannel mechanism and job packages parallel scheduling, which ensures the synchronization between the processing of the dependent job packages and parallel packages and hides the processing of the independent job package in the processing of the dependent job package. Prototyping experiments prove that this model can realize the correct and rapid processing of multiservice cross-data streams. Increasing the pipeline depth and improving the processing performance in each stage of the pipeline are the key to improving the system performance.

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An FPGA implementation and performance evaluation of the seed block cipher

Cited by 4 publications

References 5 publications

8‐bit serialised architecture of SEED block cipher for constrained devices

8‐bit serialised architecture of SEED block cipher for constrained devices

Pseudo Random Binary Sequences Obtained Using Novel Chaos Based Key Stream Generator and their Auto-correlation Properties

An Efficient Stream Data Processing Model for Multiuser Cryptographic Service

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