An FPGA implementation of a neural optimization of block truncation coding for image/video compression

Saif, Sherif M.; Abbas, Hazem M.; Nassar, Salwa M.; Wahdan, Abdelmonem A.

doi:10.1016/j.micpro.2006.02.004

Cited by 11 publications

(4 citation statements)

References 18 publications

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“…Several FPGA implementations of ANNs have been reported in the literature [1][2][3][4][5]. Of special interest is the FPGA design proposed by Leiner et al [1], because it implements the same Hopfield neural model.…”

Section: Performance and Comparison With Previous Workmentioning

confidence: 99%

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An Optimal Implementation on FPGA of a Hopfield Neural Network

Mansour

Ayoubi

Ziade

et al. 2011

Advances in Artificial Neural Systems

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The associative Hopfield memory is a form of recurrent Artificial Neural Network (ANN) that can be used in applications such as pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper presents the implementation of the Hopfield Neural Network (HNN) parallel architecture on a SRAM-based FPGA. The main advantage of the proposed implementation is its high performance and cost effectiveness: it requires O(1) multiplications and O(log N) additions, whereas most others require O(N) multiplications and O(N) additions.

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Section: Performance and Comparison With Previous Workmentioning

confidence: 99%

“…Artificial Neural Networks (ANN's) have become a subject of very dynamic and extensive research [1][2][3][4]. One important factor is the progress in VLSI technology, which makes easier the implementation and testing of ANNs in ways not available in the past.…”

Section: Introductionmentioning

confidence: 99%

An Optimal Implementation on FPGA of a Hopfield Neural Network

Mansour

Ayoubi

Ziade

et al. 2011

Advances in Artificial Neural Systems

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“…Those works usually aimed to approach the resolution of a target problem, such as, image pattern recognition [10], identification of DNA motifs [11], or video compression 2 Advances in Artificial Neural Systems [12] and only few studies concentrated on the peculiar features about FPGA implementations of HNN [13], which, unlike others neural architectures, is fully connected.…”

Section: Introductionmentioning

confidence: 99%

Architecture Analysis of an FPGA-Based Hopfield Neural Network

Sousa

Horta

Kofuji

et al. 2014

Advances in Artificial Neural Systems

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Interconnections between electronic circuits and neural computation have been a strongly researched topic in the machine learning field in order to approach several practical requirements, including decreasing training and operation times in high performance applications and reducing cost, size, and energy consumption for autonomous or embedded developments. Field programmable gate array (FPGA) hardware shows some inherent features typically associated with neural networks, such as, parallel processing, modular executions, and dynamic adaptation, and works on different types of FPGA-based neural networks were presented in recent years. This paper aims to address different aspects of architectural characteristics analysis on a Hopfield Neural Network implemented in FPGA, such as maximum operating frequency and chip-area occupancy according to the network capacity. Also, the FPGA implementation methodology, which does not employ multipliers in the architecture developed for the Hopfield neural model, is presented, in detail.

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“…FPGAs have high speed and many facilities, but because of high cost, are not acceptable in many applications. One of these implemented algorithms is block truncation coding (BTC) [5], [6]. BTC is a simple and effective technique for image compression that applies lossy compression principles [7].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Very Low Cost Surveillance System

Dadashi¹,

Dadashi²

2012

IJMLC

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Block truncation coding is an image compression algorithm that has lower efficiency in compare with some other algorithms, but also has low cost and complexity. FPGAs are used for implementing fast digital systems, but they have more cost. In this paper, a surveillance system is designed and implemented based on the BTC image compression algorithm using some parallel microcontrollers that has very low cost and suitable speed. Index Terms-BTC; motion detection; AVR microcontroller; division Compression Unit 2 Compression Unit 3 Compression Unit 4 Store Unit 1 Store Unit 2 Motion Detection Unit Control Unit Compression Unit 1

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An FPGA implementation of a neural optimization of block truncation coding for image/video compression

Cited by 11 publications

References 18 publications

An Optimal Implementation on FPGA of a Hopfield Neural Network

An Optimal Implementation on FPGA of a Hopfield Neural Network

Architecture Analysis of an FPGA-Based Hopfield Neural Network

Design and Implementation of a Very Low Cost Surveillance System

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