2006 6th International Workshop on System on Chip for Real Time Applications 2006
DOI: 10.1109/iwsoc.2006.348230
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An FPGA Implementation of a Hopfield Optimized Block Truncation Coding

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Cited by 3 publications
(3 citation statements)
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“…Several FPGA implementations of ANNs have been reported in the literature [1][2][3][4][5]. Of special interest is the FPGA design proposed by Leiner et al [1], because it implements the same Hopfield neural model.…”
Section: Performance and Comparison With Previous Workmentioning
confidence: 99%
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“…Several FPGA implementations of ANNs have been reported in the literature [1][2][3][4][5]. Of special interest is the FPGA design proposed by Leiner et al [1], because it implements the same Hopfield neural model.…”
Section: Performance and Comparison With Previous Workmentioning
confidence: 99%
“…Artificial Neural Networks (ANN's) have become a subject of very dynamic and extensive research [1][2][3][4]. One important factor is the progress in VLSI technology, which makes easier the implementation and testing of ANNs in ways not available in the past.…”
Section: Introductionmentioning
confidence: 99%
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