An FPGA Implementation of a HOG-based Object Detection Processor

Mizuno, Kosuke; Terachi, Yosuke; Takagi, Kenta; Izumi, Shintaro; Kawaguchi, Hiroshi; Yoshimoto, Masahiko

doi:10.2197/ipsjtsldm.6.42

Cited by 14 publications

(8 citation statements)

References 9 publications

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“…Thus the proposed HSG-HIK framework is proved to be a better candidate than HOG-Linear SVM for incorporation in advanced pedestrian detection systems employing hybrid features and cascaded detectors. Bauer et al [72] Kosuke et al [75,76] Proposed He received the Most Excellent Design Award, and Special Feature Award in the University Design Contest in the ASP-DAC 1997 and 1998, respectively. He received the Best Paper Awards in the 36th DAC held in New Orleans, LA, the 10th ICSPAT, Orlando, FL, in September 1999, and the 1999 ICCD Austin, TX.…”

Section: Discussionmentioning

confidence: 99%

“…The proposed HSG feature on the other hand consumes very few logic resources in comparison as shown in Table 2. Compared to a single scale HOG implementation by Kosuke et al [75,76] on same Altera platform, our implementation of HSG-HIK framework using HW-SW co-design consumes less than 40% logic resources and no dedicated DSP blocks of FPGA. FPGA implementation results of another design on a Xilinx Spartan III device by Bauer et al [72] also demonstrate the relatively higher hardware complexity of HOG based human detector.…”

Section: Fig 15 Orientation Histogram Generation Based On Above Avementioning

confidence: 95%

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A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems

Bilal

Khan

et al. 2017

IEEE Trans. Circuits Syst. Video Technol.

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Pedestrian detection is a key problem in computer vision and is currently addressed with increasingly complex solutions involving compute-intensive features and classification schemes. In this scope, Histogram of Oriented Gradients (HOG) in conjunction with linear SVM classifier is considered to be the single most discriminative feature which has been adopted as a stand-alone detector as well as a key instrument in advance systems involving hybrid features and cascaded detectors. In this paper, we propose a pedestrian detection framework which is computationally less expensive as well as more accurate than HOG-linear SVM. The proposed scheme exploits the discriminating power of the locally significant gradients in building orientation histograms without involving complex floating point operations while computing the feature. The integeronly feature allows the use of powerful Histogram Intersection Kernel SVM classifier in a fast look-up table based implementation. Resultantly, the proposed framework achieves at least 3% more accurate detection results than HOG on standard datasets while being 1.8 and 2.6 times faster on conventional desktop PC and embedded ARM platforms respectively for a single scale pedestrian detection on VGA resolution video. Additionally, hardware implementation on Altera Cyclone IV FPGA results in more than 40% savings in logic resources compared to its HOG-Linear SVM competitor. Hence, the proposed feature and classification setup is shown to be a better candidate as the single most discriminative pedestrian detector than currently accepted HOG-linear SVM.

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Section: Discussionmentioning

confidence: 99%

Section: Fig 15 Orientation Histogram Generation Based On Above Avementioning

confidence: 95%

A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems

Bilal

Khan

et al. 2017

IEEE Trans. Circuits Syst. Video Technol.

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“…Research of HOG2D for object detection in FPGAs includes [61], [62], [63], [64], [65], [66]. When processing images size 640 × 480, these designs achieve throughputs ranging from 30 fps up to 526 fps although the work in [64] processes higher resolution images at the expense of lower throughput.…”

Section: F Comparison With Other Workmentioning

confidence: 99%

Heterogeneous Acceleration of HAR Applications

Rodriguez-Borbon

Roy-Chowdhury

et al. 2020

IEEE Trans. Circuits Syst. Video Technol.

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Human action recognition (HAR) is an important field of research that intercepts with areas such as image processing, computer vision, and the design of fast algorithms, among others. HAR has several important applications including healthcare monitoring, security and surveillance, assisted living, smart homes, and video search and indexing. Despite recent developments in the field, major challenges remain. For instance, HAR is computationally expensive. Tasks such as video preprocessing, feature extraction, feature quantization, and feature classification require the execution of millions of arithmetic operations for a video sequence lasting a few seconds. To address these problems, we propose a heterogeneous approach that is based on an extensive algorithmic and experimental analysis of the histogram of gradients (HOG3D) application. We divide the application into four stages and evaluate each on CPU, GPU, and FPGA platforms. Our heterogeneous design combines the strengths of both FPGA and GPU platforms, and achieves a 1.3X speedup compared with a state-of-the-art GPU while being 1.5X more energy efficient than other homogeneous solutions, including FPGA-based designs. Moreover, our heterogeneous HAR design using fixed-point arithmetic has comparable accuracy to those of HAR algorithms using single precision floating point arithmetic.

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“…SVM is an accurate classifiers that is based on a solid theoretical background for hardware implementation [3], [4]. Some applications that have benefited from SVM hardware acceleration are pedestrian detection [5], face detection [6] and object detection [7]. SVM has also been deployed for medical application such as cardiac arrhythmia detection [8].…”

Section: Introductionmentioning

confidence: 99%

Reconfigurable Logic Embedded Architecture of Support Vector Machine Linear Kernel

Sirkunan¹,

Shaikh-Husin²,

Andromeda³

et al. 2017

EECSI

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Support Vector Machine (SVM) is a linear binary classifier that requires a kernel function to handle non-linear problems. Most previous SVM implementations for embedded systems in literature were built targeting a certain application; where analyses were done through comparison with software implementations only. The impact of different application datasets towards SVM hardware performance were not analyzed. In this work, we propose a parameterizable linear kernel architecture that is fully pipelined. It is prototyped and analyzed on Altera Cyclone IV platform and results are verified with equivalent software model. Further analysis is done on determining the effect of the number of features and support vectors on the performance of the hardware architecture. From our proposed linear kernel implementation, the number of features determine the maximum operating frequency and amount of logic resource utilization, whereas the number of support vectors determines the amount of on-chip memory usage and also the throughput of the system.

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An FPGA Implementation of a HOG-based Object Detection Processor

Cited by 14 publications

References 9 publications

A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems

A Low-Complexity Pedestrian Detection Framework for Smart Video Surveillance Systems

Heterogeneous Acceleration of HAR Applications

Reconfigurable Logic Embedded Architecture of Support Vector Machine Linear Kernel

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